Add sequencer and first examples

* sequencer for easy waveform generation of
  simple 1 bit std_logic signals
* Package with sequencer component delaration
* Examples for always & never operator

src/pkg.vhd

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+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+package pkg is
+
+
+  component sequencer is
+    generic (
+      seq : string
+    );
+    port (
+      clk  : in  std_logic;
+      data : out std_logic
+    );
+  end component sequencer;
+
+
+end package pkg;

src/psl_always.vhd

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+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_always is
+  port (
+    clk : in std_logic
+  );
+end entity psl_always;
+
+
+architecture psl of psl_always is
+
+  signal a : std_logic;
+
+begin
+
+
+  SEQ : sequencer generic map ("_-_-_") port map (clk, a);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- Signal a has to be low at cycle 0 only
+  WITHOUT_ALWAYS_a : assert a;
+
+  -- Signal a has to be low forever
+  WITH_ALWAYS_a : assert always a;
+
+
+end architecture psl;

src/psl_never.vhd

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+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_never is
+  port (
+    clk : in std_logic
+  );
+end entity psl_never;
+
+
+architecture psl of psl_never is
+
+  signal a : std_logic;
+
+begin
+
+
+  SEQ : sequencer generic map ("_-_-_") port map (clk, a);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- Signal a has to be low forever
+  NEVER_a : assert never a;
+
+  -- Equivalent assert with always and negation
+  ALWAYS_a : assert always not a;
+
+
+end architecture psl;

src/sequencer.vhd

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+library ieee;
+  use ieee.std_logic_1164.all;
+
+
+entity sequencer is
+  generic (
+    seq : string
+  );
+  port (
+    clk  : in  std_logic;
+    data : out std_logic
+  );
+end entity sequencer;
+
+
+architecture rtl of sequencer is
+
+  signal cycle : natural := 0;
+  signal ch    : character;
+
+begin
+
+
+  process (clk) is
+  begin
+    if rising_edge(clk) then
+      if (cycle < seq'length) then
+        cycle <= cycle + 1;
+      end if;
+    end if;
+  end process;
+
+  ch <= seq(cycle+1);
+
+  data <= '0' when ch = '0' or ch = '_' else
+          '1' when ch = '1' or ch = '-' else
+          'X';
+
+
+end architecture rtl;