Add example for next_event[n] operator

* Add example for next_event[n] operator
* Add formal test for next_event[n] operator
* Add next_event[n] to supported list
* Add next_event_a[n] & next_event_e[n] to unsupported list

README.md

@@ -17,10 +17,13 @@ The next two lists will grow during furter development
 * never operator
 * implication operator
 * next operator
-* next[i] operator
-* next_event() operator
+* next[n] operator
+* next_event operator
+* next_event[n] operator
 
 ## PSL features currently unsupported by GHDL:
 
 * next_a[i:j] operator
 * next_e[i:j] operator
+* next_event_a[i:j] operator
+* next_event_e[i:j] operator

formal/psl_next_event_4.sby

@@ -0,0 +1,18 @@
+[tasks]
+prove
+
+[options]
+depth 25
+prove: mode bmc
+
+[engines]
+prove: smtbmc z3
+
+[script]
+prove: ghdl --std=08 pkg.vhd sequencer.vhd psl_next_event_4.vhd -e psl_next_event_4
+prep -top psl_next_event_4
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_next_event_4.vhd

formal/tests.mk

@@ -3,4 +3,5 @@ psl_always \
 psl_never \
 psl_next \
 psl_next_3 \
-psl_next_event
+psl_next_event \
+psl_next_event_4

src/psl_next_event_4.vhd

@@ -0,0 +1,34 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_next_event_4 is
+  port (
+    clk : in std_logic
+  );
+end entity psl_next_event_4;
+
+
+architecture psl of psl_next_event_4 is
+
+  signal a, b, c : std_logic;
+  signal d, e, f : std_logic;
+
+begin
+
+  --                              0123456789012345
+  SEQ_A : sequencer generic map ("_-_____-________") port map (clk, a);
+  SEQ_B : sequencer generic map ("__----___--__-_-") port map (clk, b);
+  SEQ_C : sequencer generic map ("_____-_________-") port map (clk, c);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  NEXT_EVENT_0_a : assert always (a -> next_event(b)[4](c));
+
+
+end architecture psl;