Add example for simple SERE

* Add example for simple SERE
* Add formal test for simple SERE example
* Restructure lists in README

README.md

@@ -15,20 +15,22 @@ You can use my [Dockerfiles for SymbiYosys & GHDL(-synth)](https://github.com/tm
 Have fun!
 
 
-The next two lists will grow during further development
+The next lists will grow during further development
 
 ## PSL features supported by GHDL:
 
+### Directives
+
 * assert directive
 * cover directive
 * assume directive (synthesis)
 * restrict directive (synthesis)
 
+### Temporal operators (LTL style)
+
 * always operator
-* before operator (GHDL crash with a specific property, see psl_before.vhd)
-* eventually! operator (simulation, synthesis produces a GHDL crash, see psl_eventually.vhd)
-* logical implication operator
 * never operator
+* logical implication operator
 * next operator
 * next[n] operator
 * next_a[i to j] operator
@@ -38,6 +40,12 @@ The next two lists will grow during further development
 * next_event_e[i to j] operator
 * until operator
 * until_ operator
+* before operator (GHDL crash with a specific property, see psl_before.vhd)
+* eventually! operator (simulation, synthesis produces a GHDL crash, see psl_eventually.vhd)
+
+### Sequential Extended Regular Expressions (SERE style)
+
+* Simple SERE
 
 ## PSL features not yet supported by GHDL:
 

formal/psl_sere.sby

@@ -0,0 +1,18 @@
+[tasks]
+prove
+
+[options]
+depth 25
+prove: mode bmc
+
+[engines]
+prove: smtbmc z3
+
+[script]
+prove: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere.vhd -e psl_sere
+prep -top psl_sere
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_sere.vhd

formal/tests.mk

@@ -12,4 +12,5 @@ psl_next_event_e \
 psl_next_event_a \
 psl_until \
 psl_before \
-psl_eventually
+psl_eventually \
+psl_sere

src/psl_sere.vhd

@@ -0,0 +1,42 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_sere is
+  port (
+    clk : in std_logic
+  );
+end entity psl_sere;
+
+
+architecture psl of psl_sere is
+
+  signal a, b : std_logic;
+
+begin
+
+
+  --                              012345
+  SEQ_A : sequencer generic map ("--____") port map (clk, a);
+  SEQ_B : sequencer generic map ("_-____") port map (clk, b);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- This assertion holds
+  SERE_0_a : assert {a};
+
+  -- This assertion holds
+  SERE_1_a : assert {a; a};
+
+  -- This assertion holds
+  SERE_2_a : assert {a; a and b};
+
+  -- This assertion doesn't hold at cycle 2
+  SERE_3_a : assert always {a; a};
+
+
+end architecture psl;