Browse Source

Add issue code for ghdl/ghdl#1591

T. Meissner 1 week ago
parent
commit
1acd5e3d6c
1 changed files with 70 additions and 0 deletions
  1. 70
    0
      issues/issue_1591.vhd

+ 70
- 0
issues/issue_1591.vhd View File

@@ -0,0 +1,70 @@
1
+library ieee;
2
+  use ieee.std_logic_1164.all;
3
+
4
+
5
+entity issue is
6
+  port (
7
+    clk : in std_logic
8
+  );
9
+end entity issue;
10
+
11
+
12
+architecture psl of issue is
13
+
14
+  signal a : boolean := true;
15
+
16
+begin
17
+
18
+
19
+  testG : if true generate
20
+
21
+    signal b : boolean := true;
22
+    signal c : boolean := false;
23
+
24
+  begin
25
+
26
+    c <= true;
27
+
28
+    -- All is sensitive to rising edge of clk
29
+    default clock is rising_edge(clk);
30
+
31
+    -- This assertion works
32
+    INITIAL_0_a : assert always a;
33
+
34
+    -- This assertion generates an ghdl-yosys-plugin error
35
+    -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
36
+    INITIAL_1_a : assert always b;
37
+
38
+    -- This assertion works
39
+    INITIAL_2_a : assert always c;
40
+
41
+  end generate testG;
42
+
43
+  -- Same error occurs when using a block instead of a generate
44
+  -- statement
45
+  testB : block is
46
+
47
+    signal b : boolean := true;
48
+    signal c : boolean := false;
49
+
50
+  begin
51
+
52
+    c <= true;
53
+
54
+    -- All is sensitive to rising edge of clk
55
+    default clock is rising_edge(clk);
56
+
57
+    -- This assertion works
58
+    INITIAL_0_a : assert always a;
59
+
60
+    -- This assertion generates an ghdl-yosys-plugin error
61
+    -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
62
+    INITIAL_1_a : assert always b;
63
+
64
+    -- This assertion works
65
+    INITIAL_2_a : assert always c;
66
+
67
+  end block testB;
68
+
69
+
70
+end architecture psl;