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Add example for named properties

T. Meissner 3 months ago
parent
commit
29ff43dcb2
4 changed files with 85 additions and 1 deletions
  1. 1
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      README.md
  2. 18
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      formal/psl_property.sby
  3. 2
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      sim/tests.mk
  4. 64
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      src/psl_property.vhd

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README.md View File

@@ -70,6 +70,7 @@ The next lists will grow during further development
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 * Partial support of PSL vunits (synthesis only)
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 * Partial support of named sequences (simulation only)
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+* Partial support of named properties (simulation only)
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 ## Not yet supported by GHDL:
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formal/psl_property.sby View File

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+[tasks]
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+bmc
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+
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+[options]
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+depth 25
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+bmc: mode bmc
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+
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+[engines]
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+bmc: smtbmc z3
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+
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+[script]
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+bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_property.vhd -e psl_property
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+prep -top psl_property
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+
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+[files]
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+../src/pkg.vhd
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+../src/sequencer.vhd
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+../src/psl_property.vhd

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- 1
sim/tests.mk View File

@@ -26,4 +26,5 @@ psl_sere_len_matching_and \
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 psl_sere_non_len_matching_and \
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 psl_sere_concat \
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 psl_sere_fusion \
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-psl_sequence
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+psl_sequence \
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+psl_property

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src/psl_property.vhd View File

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+library ieee;
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+  use ieee.std_logic_1164.all;
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+
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+use work.pkg.all;
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+
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+
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+entity psl_property is
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+  port (
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+    clk : in std_logic
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+  );
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+end entity psl_property;
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+
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+
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+architecture psl of psl_property is
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+
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+  signal req, avalid, busy, adone, data, ddone : std_logic;
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+
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+begin
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+
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+
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+  --                                   01234567890123
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+  SEQ_REQ    : sequencer generic map ("_-____________") port map (clk, req);
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+  SEQ_AVALID : sequencer generic map ("__-___________") port map (clk, avalid);
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+  SEQ_BUSY   : sequencer generic map ("___-_--_______") port map (clk, busy);
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+  SEQ_ADONE  : sequencer generic map ("_______-______") port map (clk, adone);
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+  SEQ_DATA   : sequencer generic map ("________---___") port map (clk, data);
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+  SEQ_DDONE  : sequencer generic map ("___________-__") port map (clk, ddone);
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+
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+
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+  -- All is sensitive to rising edge of clk
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+  default clock is rising_edge(clk);
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+
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+  -- Transfer property
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+  -- Don't works in synthesis, only in simulation
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+  property transfer_3 is always (
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+    {req} |=> {{avalid; busy[->3]; adone}; {data[->3]; ddone}}
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+  );
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+
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+  -- SERE concatenation operator
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+  -- RHS starts at one cycle cycle that the LHS ends
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+  -- This assertion holds
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+  PROP_0_a : assert transfer_3;
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+
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+  -- Properties can have parameters
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+  -- Don't works in synthesis, only in simulation
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+  -- Parameters with repetition operators lead to crash:
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+  -- raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : no field Hash
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+  property transfer_3_p (boolean v, ad, dd) is always (
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+    {req} |=> {{v; busy[->3]; ad}; {data[->3]; dd}}
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+  );
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+
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+  -- SERE concatenation operator
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+  -- RHS starts at one cycle cycle that the LHS ends
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+  -- This assertion holds
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+  PROP_1_a : assert transfer_3_p(avalid, adone, ddone);
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+
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+  -- Stop simulation after longest running sequencer is finished
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+  -- Simulation only code by using pragmas
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+  -- synthesis translate_off
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+  stop_sim(clk, 13);
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+  -- synthesis translate_on
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+
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+
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+end architecture psl;