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Add simulation of the PSL examples, fixes #1

master
T. Meissner 5 years ago
parent
commit
4308f7d966
3 changed files with 73 additions and 0 deletions
  1. +24
    -0
      sim/Makefile
  2. +24
    -0
      sim/template.vhd
  3. +25
    -0
      sim/tests.mk

+ 24
- 0
sim/Makefile View File

@ -0,0 +1,24 @@
include tests.mk
VHD_STD := 08
.PHONY: all clean
.SECONDARY:
all: ${psl_tests}
%: ../src/%.vhd ../src/pkg.vhd ../src/sequencer.vhd ../src/hex_sequencer.vhd work/%/testbench.vhd
ghdl -a --std=$(VHD_STD) --workdir=work/$@ ../src/pkg.vhd ../src/sequencer.vhd ../src/hex_sequencer.vhd
ghdl -a --std=$(VHD_STD) --workdir=work/$@ ../src/$@.vhd
ghdl -a --std=$(VHD_STD) --workdir=work/$@ work/$@/testbench.vhd
ghdl -e --std=$(VHD_STD) --workdir=work/$@ -o work/$@/tb_$@ tb_$@
cd work/$@; ghdl -r --std=$(VHD_STD) tb_$@ --wave=$@.ghw --psl-report=$@_psl_coverage.json --stop-time=50ns
work/%/testbench.vhd: template.vhd
mkdir -p work; mkdir -p $(dir $@)
sed 's/__DUT__/$(subst /,,$(subst work,,$(dir $@)))/g' $< > $@
clean:
rm -rf work

+ 24
- 0
sim/template.vhd View File

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library ieee;
use ieee.std_logic_1164.all;
entity tb___DUT__ is
end entity tb___DUT__;
architecture sim of tb___DUT__ is
signal clk : std_logic := '1';
signal cycle : natural := 0;
begin
clk <= not clk after 1 ns;
cycle <= cycle + 1 when rising_edge(clk);
DUT : entity work.__DUT__(psl) port map (clk);
end architecture sim;

+ 25
- 0
sim/tests.mk View File

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psl_tests := \
psl_always \
psl_logical_implication \
psl_never \
psl_next \
psl_next_3 \
psl_next_a \
psl_next_e \
psl_next_event \
psl_next_event_4 \
psl_next_event_e \
psl_next_event_a \
psl_until \
psl_before \
psl_eventually \
psl_sere \
psl_sere_overlapping_suffix_impl \
psl_sere_non_overlapping_suffix_impl \
psl_sere_consecutive_repetition \
psl_sere_non_consecutive_repeat_repetition \
psl_sere_non_consecutive_goto_repetition \
psl_cover \
psl_sere_within \
psl_sere_or \
psl_sere_len_matching_and

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