Add example for SERE non-length-matching and (&) operator

README.md

@@ -52,6 +52,7 @@ The next lists will grow during further development
 * Non consecutive repetition operator (`[=n]`, `[=i to j]`)
 * Non consecutive goto repetition operator (`[->]`, `[->n]`, `[->i to j]`)
 * Length-matching and operator (`&&`)
+* Non-length-matching and operator (`&`)
 * or operator (`|`)
 * `within` operator
 
@@ -63,7 +64,7 @@ The next lists will grow during further development
 
 * `forall` statement
 * Synthesis of strong operator versions
-* PSL functions (`prev()` partially implemented)
+* PSL functions (`prev()` implemented)
 
 ## Under investigation
 

formal/psl_sere_non_len_matching_and.sby

@@ -0,0 +1,18 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_non_len_matching_and.vhd -e psl_sere_non_len_matching_and
+prep -top psl_sere_non_len_matching_and
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_sere_non_len_matching_and.vhd

formal/tests.mk

@@ -23,4 +23,5 @@ psl_cover \
 psl_sere_within \
 psl_sere_or \
 psl_sere_len_matching_and \
+psl_sere_non_len_matching_and \
 psl_prev

sim/tests.mk

@@ -22,4 +22,5 @@ psl_sere_non_consecutive_goto_repetition \
 psl_cover \
 psl_sere_within \
 psl_sere_or \
-psl_sere_len_matching_and
+psl_sere_len_matching_and \
+psl_sere_non_len_matching_and

src/psl_sere_non_len_matching_and.vhd

@@ -0,0 +1,46 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_sere_non_len_matching_and is
+  port (
+    clk : in std_logic
+  );
+end entity psl_sere_non_len_matching_and;
+
+
+architecture psl of psl_sere_non_len_matching_and is
+
+  signal req, done0, done1, done2, ack : std_logic;
+
+begin
+
+
+  --                                  01234567890
+  SEQ_REQ   : sequencer generic map ("_-_________") port map (clk, req);
+  SEQ_DONE0 : sequencer generic map ("______-____") port map (clk, done0);
+  SEQ_DONE1 : sequencer generic map ("________-__") port map (clk, done1);
+  SEQ_DONE2 : sequencer generic map ("____-______") port map (clk, done2);
+  SEQ_ACK   : sequencer generic map ("_________-_") port map (clk, ack);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- Non length matching AND three SERE
+  -- Each of done0, done1 & done2 has to hold a cycle after
+  -- req holded. Transfer is ended by ack holding one cycle
+  -- after last done holded
+  -- This assertion holds
+  SERE_0_a : assert always {req} |=> {{done0[->] & done1[->] & done2[->]}; ack};
+
+  -- Stop simulation after longest running sequencer is finished
+  -- Simulation only code by using pragmas
+  -- synthesis translate_off
+  stop_sim(clk, 11);
+  -- synthesis translate_on
+
+
+end architecture psl;