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@ -1,5 +1,6 @@ |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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use work.pkg.all; |
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@ -13,17 +14,22 @@ end entity psl_prev; |
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architecture psl of psl_prev is |
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signal valid : std_logic; |
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signal a : std_logic; |
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signal d : std_logic_vector(3 downto 0); |
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signal valid : std_logic; |
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signal a : std_logic; |
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signal di, do : std_logic_vector(3 downto 0); |
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signal cnt : std_logic_vector(3 downto 0); |
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begin |
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-- 01234567890123 |
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SEQ_VALID : sequencer generic map ("____-_-_-_-_-_") port map (clk, valid); |
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SEQ_A : sequencer generic map ("-__--__--__--_") port map (clk, a); |
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SEQ_D : hex_sequencer generic map ("00011223344556") port map (clk, d); |
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-- 01234567890123 |
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SEQ_VALID : sequencer generic map ("____-_-_-_-_-_") port map (clk, valid); |
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SEQ_A : sequencer generic map ("-__--__--__--_") port map (clk, a); |
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SEQ_DI : hex_sequencer generic map ("00011223344556") port map (clk, di); |
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SEQ_DO : hex_sequencer generic map ("00001020304050") port map (clk, do); |
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SEQ_CNT : hex_sequencer generic map ("0123456789ABCDEF") port map (clk, cnt); |
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-- All is sensitive to rising edge of clk |
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@ -33,22 +39,21 @@ begin |
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PREV_0_a : assert always (valid -> a = prev(a)); |
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-- This assertion should hold |
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-- prev() with vector parameter isn't supported yet |
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-- Workaround: VHDL glue logic and simple compare |
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-- PREV_1_a : assert always (valid -> d = prev(d)); |
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PREV_1_a : assert always (valid -> di = prev(di)); |
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-- Workaround with VHDL glue logic generating the |
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-- previous value of d and simple comparing the two values |
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-- Workaround needed before prev() was implemented |
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-- With VHDL glue logic generating the |
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-- previous value of di and simple comparing the two values |
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d_reg : block is |
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signal d_prev : std_logic_vector(d'range); |
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signal di_prev : std_logic_vector(di'range); |
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begin |
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process (clk) is |
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begin |
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if rising_edge(clk) then |
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d_prev <= d; |
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di_prev <= di; |
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end if; |
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end process; |
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PREV_2_a : assert always (valid -> d = d_prev); |
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PREV_2_a : assert always (valid -> di = di_prev); |
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end block d_reg; |
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-- Using prev() with additional parameter i, should return |
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@ -62,6 +67,15 @@ begin |
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-- This assertion holds |
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PREV_4_a : assert always (valid -> a = prev(a, 4)); |
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-- Some kind of pipeline data check, checks if do is |
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-- equal to di one cycle before when valid holds |
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-- This assertion holds |
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PREV_5_a : assert always (valid -> do = prev(di, 1)); |
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-- Example for a simple counter check |
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-- This assertion holds |
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PREV_6_a : assert always ((cnt /= x"F") -> next (unsigned(cnt) = unsigned(prev(cnt)) + 1)); |
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-- Stop simulation after longest running sequencer is finished |
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-- Simulation only code by using pragmas |
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-- synthesis translate_off |
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