Add example for SERE length mathcing and (&&) operator

formal/psl_sere_len_matching_and.sby

@@ -0,0 +1,18 @@
+[tasks]
+bmc
+
+[options]
+depth 25
+bmc: mode bmc
+
+[engines]
+bmc: smtbmc z3
+
+[script]
+bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_sere_len_matching_and.vhd -e psl_sere_len_matching_and
+prep -top psl_sere_len_matching_and
+
+[files]
+../src/pkg.vhd
+../src/sequencer.vhd
+../src/psl_sere_len_matching_and.vhd

formal/tests.mk

@@ -21,4 +21,5 @@ psl_sere_non_consecutive_repeat_repetition \
 psl_sere_non_consecutive_goto_repetition \
 psl_cover \
 psl_sere_within \
-psl_sere_or
+psl_sere_or \
+psl_sere_len_matching_and

src/psl_sere_len_matching_and.vhd

@@ -0,0 +1,38 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+use work.pkg.all;
+
+
+entity psl_sere_len_matching_and is
+  port (
+    clk : in std_logic
+  );
+end entity psl_sere_len_matching_and;
+
+
+architecture psl of psl_sere_len_matching_and is
+
+  signal req, busy, valid, done : std_logic;
+
+begin
+
+
+  --                                  0123456789
+  SEQ_REQ   : sequencer generic map ("_-________") port map (clk, req);
+  SEQ_BUSY  : sequencer generic map ("__------__") port map (clk, busy);
+  SEQ_VALID : sequencer generic map ("___-_-_-__") port map (clk, valid);
+  SEQ_DONE  : sequencer generic map ("________-_") port map (clk, done);
+
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- Length matching AND two SERE
+  -- valid has to hold 3 times between req & done.
+  -- busy has to hold each cycle between req & done.
+  -- This assertion holds
+  SERE_0_a : assert always {req} |=> {{valid[->3]} && {(busy and not done)[+]}; not busy and done};
+
+
+end architecture psl;

src/psl_sere_or.vhd

@@ -14,7 +14,7 @@ end entity psl_sere_or;
 architecture psl of psl_sere_or is
 
   signal req2, req4, busy, valid, done : std_logic;
-  signal req, wen, ren, ends           : std_logic;
+  signal req, wen, ends                : std_logic;
 
 begin