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@ -21,8 +21,7 @@ end entity hex_sequencer; |
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architecture rtl of hex_sequencer is |
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signal cycle : natural := 0; |
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signal ch : character; |
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signal index : natural := seq'low; |
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begin |
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@ -30,15 +29,13 @@ begin |
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process (clk) is |
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begin |
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if rising_edge(clk) then |
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if (cycle < seq'length) then |
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cycle <= cycle + 1; |
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if (index < seq'high) then |
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index <= index + 1; |
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end if; |
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end if; |
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end process; |
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ch <= seq(cycle+1); |
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data <= to_hex(ch); |
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data <= to_hex(seq(index)); |
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end architecture rtl; |