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Add PSL vunit inherit example as ghdl/ghdl#1899 was fixed

* New example of PSL inherit usage
* Add example to formal tests
* Add issue_1899 to issues tests
* Add inherit to README
master
T. Meissner 3 years ago
parent
commit
ed269c05ed
6 changed files with 79 additions and 1 deletions
  1. +1
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      README.md
  2. +19
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      formal/psl_vunit_inherit.sby
  3. +1
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      formal/tests.mk
  4. +2
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      issues/tests.mk
  5. +23
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      src/psl_vunit_inherit.psl
  6. +33
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      src/psl_vunit_inherit.vhd

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README.md View File

@ -80,6 +80,7 @@ The next lists will grow during further development
* Partial support of named sequences (some parameter types missing) * Partial support of named sequences (some parameter types missing)
* Partial support of named properties (some parameter types missing) * Partial support of named properties (some parameter types missing)
* Partial support of PSL `endpoint` (simulation only, in PSL comments) * Partial support of PSL `endpoint` (simulation only, in PSL comments)
* vunit inhiterance (`inherit`, synthesis only)
### Yosys formal extensions (reference to [Symbiyosys docs](https://symbiyosys.readthedocs.io/en/latest/verilog.html#unconstrained-variables)) ### Yosys formal extensions (reference to [Symbiyosys docs](https://symbiyosys.readthedocs.io/en/latest/verilog.html#unconstrained-variables))


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formal/psl_vunit_inherit.sby View File

@ -0,0 +1,19 @@
[tasks]
bmc
[options]
depth 25
bmc: mode bmc
[engines]
bmc: smtbmc z3
[script]
bmc: ghdl --std=08 pkg.vhd sequencer.vhd psl_vunit_inherit.vhd psl_vunit_inherit.psl -e psl_vunit_inherit
prep -top psl_vunit_inherit
[files]
../src/pkg.vhd
../src/sequencer.vhd
../src/psl_vunit_inherit.vhd
../src/psl_vunit_inherit.psl

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formal/tests.mk View File

@ -36,6 +36,7 @@ psl_fell \
psl_onehot \ psl_onehot \
psl_onehot0 \ psl_onehot0 \
psl_vunit \ psl_vunit \
psl_vunit_inherit \
yosys_anyconst \ yosys_anyconst \
yosys_anyseq \ yosys_anyseq \
psl_abort psl_abort

+ 2
- 1
issues/tests.mk View File

@ -11,4 +11,5 @@ issue_1372 \
issue_1591 \ issue_1591 \
issue_1658 \ issue_1658 \
issue_1832 \ issue_1832 \
issue_1850
issue_1850 \
issue_1899

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src/psl_vunit_inherit.psl View File

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vunit psl_vunit_inherit_0_vu {
-- Named sequences
sequence s_a (boolean data) is {data; data};
sequence s_b (boolean data) is {data};
}
vunit psl_vunit_inherit_vu (psl_vunit_inherit(beh)) {
inherit psl_vunit_inherit_0_vu;
-- All is sensitive to rising edge of clk
default clock is rising_edge(clk);
-- This assertion holds
SERE_0_a : assert always s_a(a) |-> s_b(b);
-- This assertion holds, similar to SERE_0_a
PROP_0_a : assert always {a; a} |-> {b};
}

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src/psl_vunit_inherit.vhd View File

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pkg.all;
entity psl_vunit_inherit is
port (
clk : in std_logic
);
end entity psl_vunit_inherit;
architecture beh of psl_vunit_inherit is
signal a, b : std_logic;
begin
-- 012345
SEQ_A : sequencer generic map ("--____") port map (clk, a);
SEQ_B : sequencer generic map ("_-____") port map (clk, b);
-- Stop simulation after longest running sequencer is finished
-- Simulation only code by using pragmas
-- synthesis translate_off
stop_sim(clk, 6);
-- synthesis translate_on
end architecture beh;

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