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23 lines
486 B
23 lines
486 B
vunit psl_vunit_inherit_0_vu {
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-- Named sequences
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sequence s_a (boolean data) is {data; data};
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sequence s_b (boolean data) is {data};
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}
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vunit psl_vunit_inherit_vu (psl_vunit_inherit(beh)) {
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inherit psl_vunit_inherit_0_vu;
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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SERE_0_a : assert always s_a(a) |-> s_b(b);
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-- This assertion holds, similar to SERE_0_a
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PROP_0_a : assert always {a; a} |-> {b};
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}
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