Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
vhdl
ghdl
psl
assertions
formal
yosys
T. Meissner 333c6f8c16 Add example for PSL endpoints (currently simulation only) 1 day ago
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Makefile Add example for PSL endpoints (currently simulation only) 1 day ago
template.vhd Stop simulation after a given number of cycles instead of time 7 months ago
tests.mk Add example for PSL endpoints (currently simulation only) 1 day ago