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24 lines
355 B
24 lines
355 B
library ieee;
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use ieee.std_logic_1164.all;
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entity tb___DUT__ is
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end entity tb___DUT__;
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architecture sim of tb___DUT__ is
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signal clk : std_logic := '1';
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signal cycle : natural := 0;
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begin
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clk <= not clk after 500 ps;
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cycle <= cycle + 1 when rising_edge(clk);
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DUT : entity work.__DUT__(psl) port map (clk);
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end architecture sim;
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