library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_sere_concat is
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port (
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clk : in std_logic
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);
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end entity psl_sere_concat;
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architecture psl of psl_sere_concat is
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signal req, avalid, busy, adone, data, ddone : std_logic;
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begin
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-- 01234567890123
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SEQ_REQ : sequencer generic map ("_-____________") port map (clk, req);
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SEQ_AVALID : sequencer generic map ("__-___________") port map (clk, avalid);
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SEQ_BUSY : sequencer generic map ("___-_--_______") port map (clk, busy);
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SEQ_ADONE : sequencer generic map ("_______-______") port map (clk, adone);
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SEQ_DATA : sequencer generic map ("________---___") port map (clk, data);
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SEQ_DDONE : sequencer generic map ("___________-__") port map (clk, ddone);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- SERE concatenation operator
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-- RHS starts at one cycle cycle that the LHS ends
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-- This assertion holds
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SERE_0_a : assert always {req} |=> {{avalid; busy[->3]; adone}; {data[->3]; ddone}};
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-- SERE concatenation operator
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-- RHS starts at one cycle cycle that the LHS ends
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-- This cover holds at cycle 7
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SERE_0_c : cover {req; avalid; busy[->3]; adone} report "Address phase completed";
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-- SERE concatenation operator
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-- RHS starts at one cycle cycle that the LHS ends
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-- This cover holds at cycle 11
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SERE_1_c : cover {data[->3]; ddone} report "Data phase completed";
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 13);
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-- synthesis translate_on
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end architecture psl;
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