Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 
 
T. Meissner 00ac16a888 Add tests for formal verification; optimizations; fixes #3 5 years ago
formal Add tests for formal verification; optimizations; fixes #3 5 years ago
src Add tests for formal verification; optimizations; fixes #3 5 years ago
LICENSE.md Initial commit: add license file 5 years ago
README.md Add tests for formal verification; optimizations; fixes #3 5 years ago

README.md

psl_with_ghdl

A collection of examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys).

The next two lists will grow during furter development

PSL features supported by GHDL:

  • assert directive
  • cover directive
  • assume directive (synthesis)
  • restrict directive (synthesis)
  • always operator
  • never operator
  • implication operator
  • next operator
  • next[i] operator
  • next_event() operator

PSL features currently unsupported by GHDL:

  • next_a[i:j] operator
  • next_e[i:j] operator