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40 lines
724 B
40 lines
724 B
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_never is
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port (
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clk : in std_logic
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);
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end entity psl_never;
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architecture psl of psl_never is
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signal a, b : std_logic;
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begin
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-- 0123
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SEQ_A : sequencer generic map ("____") port map (clk, a);
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SEQ_B : sequencer generic map ("__-_") port map (clk, b);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- This assertion holds
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NEVER_0_a : assert never a;
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-- Equivalent assert with always and negation
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-- This assertion holds
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ALWAYS_a : assert always not a;
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-- This assertion doesn't hold at cycle 2
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NEVER_1_a : assert never b;
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end architecture psl;
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