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57 lines
960 B
57 lines
960 B
library ieee;
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use ieee.std_logic_1164.all;
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entity issue is
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port (
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clk : in std_logic
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);
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end entity issue;
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architecture psl of issue is
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attribute anyconst : boolean;
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signal a: natural;
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attribute anyconst of a : signal is true;
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begin
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- works
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assume always a = 42;
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assert always a = 42;
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-- Error occurs when using a generate statement
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testG : if true generate
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signal b : natural;
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attribute anyconst of b : signal is true;
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begin
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-- works
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GEN_ASSUME : assume always b = 23;
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GEN_ASSERT : assert always b = 23;
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end generate testG;
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-- Same error occurs when using a block statement
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testB : block is
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signal c : natural;
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attribute anyconst of c : signal is true;
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begin
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-- works
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BLK_ASSUME : assume always c = 11;
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BLK_ASSERT : assert always c = 11;
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end block testB;
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end architecture psl;
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