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50 lines
1.1 KiB
50 lines
1.1 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use work.pkg.all;
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entity psl_always is
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port (
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clk : in std_logic
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);
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end entity psl_always;
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architecture psl of psl_always is
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signal a : std_logic;
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begin
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-- 012345
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SEQ : sequencer generic map ("--____") port map (clk, a);
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-- All is sensitive to rising edge of clk
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default clock is rising_edge(clk);
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-- Beware: potential pitfall!
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-- Every time a PSL assertion is similar to a concurrent
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-- VHDL assertion at that place, it is interpreted as such
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-- This assert is considered as VHDL assert statement,
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-- so it is active every cycle
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-- This assertion doesn't hold at cycle 2
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VHDL_ASSERT_a : assert a;
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-- The PSL comment helps to mark this as PSL assert
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-- This assertion holds
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-- psl WITHOUT_ALWAYS_a : assert a;
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-- This assertion doesn't hold at cycle 2
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WITH_ALWAYS_a : assert always a;
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-- Stop simulation after longest running sequencer is finished
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-- Simulation only code by using pragmas
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-- synthesis translate_off
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stop_sim(clk, 6);
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-- synthesis translate_on
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end architecture psl;
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