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fixed swapped clk & rst connections on WishBoneMasterE module

master
T. Meissner 10 years ago
parent
0614c3eefd
commit
91306866a9
1 changed files with 2 additions and 2 deletions
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  1. +2
    -2
      raspiFpga/src/RaspiFpgaE.vhd

+ 2
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raspiFpga/src/RaspiFpgaE.vhd View File

@ -209,8 +209,8 @@ begin
) )
port map ( port map (
--+ wishbone system if --+ wishbone system if
WbRst_i => s_wb_clk,
WbClk_i => s_wb_rst,
WbRst_i => s_wb_rst,
WbClk_i => s_wb_clk,
--+ wishbone outputs --+ wishbone outputs
WbCyc_o => s_wb_cyc, WbCyc_o => s_wb_cyc,
WbStb_o => s_wb_stb, WbStb_o => s_wb_stb,


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