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add LUT implementation of FiRo

master
T. Meissner 7 years ago
parent
commit
ee5b5cc594
2 changed files with 31 additions and 4 deletions
  1. +28
    -3
      raspiFpga/src/FiRoE.vhd
  2. +3
    -1
      raspiFpga/src/RaspiFpgaE.vhd

+ 28
- 3
raspiFpga/src/FiRoE.vhd View File

@ -2,11 +2,15 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library machxo2;
use machxo2.components.all;
entity FiRoE is
generic (
TOGGLE : boolean := true
IMP : string := "HDL",
TOGGLE : boolean := true
);
port (
FiRo_o : out std_logic;
@ -38,12 +42,33 @@ architecture rtl of FiRoE is
begin
FiroRingG : for index in 1 to 15 generate
FiroRingG : for index in 0 to 30 generate
HdlG : if IMP = "HDL" generate
s_ring(index) <= not(s_ring(index - 1));
end generate HdlG;
s_ring(index) <= not(s_ring(index - 1));
LutG : if IMP = "LUT" generate
lut : LUT4
generic map (
init => x"FFFF"
)
port map (
Z => s_ring(i-1),
A => s_ring(i),
B => '0',
C => '0',
D => '0'
);
end generate LutG;
end generate FiroRingG;
s_ring(0) <= (s_ring(15) xor s_ring(14) xor s_ring(7) xor s_ring(6) xor s_ring(5) xor s_ring(4) xor s_ring(2)) and Run_i;


+ 3
- 1
raspiFpga/src/RaspiFpgaE.vhd View File

@ -105,7 +105,8 @@ architecture rtl of RaspiFpgaE is
component FiRoE is
generic (
TOGGLE : boolean := true
IMP : string := "HDL",
TOGGLE : boolean := true
);
port (
FiRo_o : out std_logic;
@ -323,6 +324,7 @@ begin
i_FiRoE : FiRoE
generic map (
IMP => "LUT",
TOGGLE => true
)
port map (


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