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add LUT implementation of FiRo

T. Meissner 5 years ago
parent
commit
ee5b5cc594
2 changed files with 31 additions and 4 deletions
  1. 28
    3
      raspiFpga/src/FiRoE.vhd
  2. 3
    1
      raspiFpga/src/RaspiFpgaE.vhd

+ 28
- 3
raspiFpga/src/FiRoE.vhd View File

@@ -2,11 +2,15 @@ library ieee;
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   use ieee.std_logic_1164.all;
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   use ieee.numeric_std.all;
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+library machxo2;
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+  use machxo2.components.all;
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+
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 entity FiRoE is
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   generic (
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-    TOGGLE   : boolean := true
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+    IMP    : string  := "HDL",
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+    TOGGLE : boolean := true
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   );
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   port (
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     FiRo_o : out std_logic;
@@ -38,12 +42,33 @@ architecture rtl of FiRoE is
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 begin
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-  FiroRingG : for index in 1 to 15 generate
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+  FiroRingG : for index in 0 to 30 generate
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+
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+    HdlG : if IMP = "HDL" generate
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+
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+      s_ring(index) <= not(s_ring(index - 1));
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+
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+    end generate HdlG;
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-    s_ring(index) <= not(s_ring(index - 1));
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+    LutG : if IMP = "LUT" generate
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+
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+      lut : LUT4
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+        generic map (
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+          init => x"FFFF"
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+        )
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+        port map (
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+          Z => s_ring(i-1),
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+          A => s_ring(i),
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+          B => '0',
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+          C => '0',
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+          D => '0'
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+        );
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+
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+      end generate LutG;
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   end generate FiroRingG;
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+
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   s_ring(0) <= (s_ring(15) xor s_ring(14) xor s_ring(7) xor s_ring(6) xor s_ring(5) xor s_ring(4) xor s_ring(2)) and Run_i;
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+ 3
- 1
raspiFpga/src/RaspiFpgaE.vhd View File

@@ -105,7 +105,8 @@ architecture rtl of RaspiFpgaE is
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   component FiRoE is
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     generic (
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-      TOGGLE   : boolean := true
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+      IMP    : string  := "HDL",
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+      TOGGLE : boolean := true
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     );
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     port (
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       FiRo_o : out std_logic;
@@ -323,6 +324,7 @@ begin
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   i_FiRoE : FiRoE
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     generic map (
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+      IMP    => "LUT",
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       TOGGLE => true
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     )
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     port map (