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62 lines
1.3 KiB
62 lines
1.3 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity CpldTestT is
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end entity CpldTestT;
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architecture rtl of CpldTestT is
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component CpldTestE is
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port (
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-- globals
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XcClk_i : in std_logic;
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-- avr
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AvrData_io : inout std_logic_vector(13 downto 0);
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AvrSck_i : in std_logic;
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AvrMosi_i : in std_logic;
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AvrMiso_o : out std_logic;
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-- spi flash
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SpfRst_n_o : out std_logic;
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SpfCs_n_o : out std_logic;
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SpfSck_o : out std_logic;
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SpfMosi_o : out std_logic;
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SpfMiso_i : in std_logic;
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-- gpio
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Gpio_io : inout std_logic_vector(4 downto 0)
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);
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end component CpldTestE;
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signal s_cpld_clk : std_logic := '0';
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signal s_cpld_gpio : std_logic_vector(4 downto 0);
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begin
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s_cpld_clk <= not(s_cpld_clk) after 20 ns;
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i_CpldTestE : CpldTestE
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port map
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(
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-- globals
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XcClk_i => s_cpld_clk,
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-- avr
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AvrData_io => open,
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AvrSck_i => '0',
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AvrMosi_i => '0',
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AvrMiso_o => open,
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-- spi flash
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SpfRst_n_o => open,
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SpfCs_n_o => open,
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SpfSck_o => open,
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SpfMosi_o => open,
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SpfMiso_i => '0',
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-- gpio
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Gpio_io => s_cpld_gpio
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);
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end architecture rtl;
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