Verification IPs for simulation & formal verification of various selected protocols. All tests are done with [GHDL](https://github.com/ghdl/ghdl) and [SymbiYosys](https://github.com/YosysHQ/SymbiYosys), a front-end for formal verification flows based on [Yosys](https://github.com/YosysHQ/yosys).
### wishbone
Simple VIP for the wishbone bus protocol. At the moment support of classic single read / write cycles only.
