cryptography ip-cores in vhdl / verilog
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9 years ago
9 years ago
  1. -- ======================================================================
  2. -- AES encryption/decryption
  3. -- algorithm according to FIPS 197 specification
  4. -- Copyright (C) 2011 Torsten Meissner
  5. -------------------------------------------------------------------------
  6. -- This program is free software; you can redistribute it and/or modify
  7. -- it under the terms of the GNU General Public License as published by
  8. -- the Free Software Foundation; either version 2 of the License, or
  9. -- (at your option) any later version.
  10. -- This program is distributed in the hope that it will be useful,
  11. -- but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. -- GNU General Public License for more details.
  14. -- You should have received a copy of the GNU General Public License
  15. -- along with this program; if not, write to the Free Software
  16. -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17. -- ======================================================================
  18. library ieee;
  19. use ieee.std_logic_1164.all;
  20. use ieee.numeric_std.all;
  21. use work.aes_pkg.all;
  22. entity aes is
  23. generic (
  24. design_type : string := "ITER"
  25. );
  26. port (
  27. reset_i : in std_logic; -- async reset
  28. clk_i : in std_logic; -- clock
  29. mode_i : in std_logic; -- aes-modus: 0 = encrypt, 1 = decrypt
  30. key_i : in std_logic_vector(0 TO 127); -- key input
  31. data_i : in std_logic_vector(0 TO 127); -- data input
  32. valid_i : in std_logic; -- input key/data valid flag
  33. accept_o : out std_logic;
  34. data_o : out std_logic_vector(0 TO 127); -- data output
  35. valid_o : out std_logic; -- output data valid flag
  36. accept_i : in std_logic
  37. );
  38. end entity aes;
  39. architecture rtl of aes is
  40. begin
  41. PipeG : if design_type = "PIPE" generate
  42. begin
  43. end generate PipeG;
  44. end architecture rtl;