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cryptocores
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cryptography ip-cores in vhdl / verilog
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cryptocores/aes/sim/vhdl/tb_aes.tcl

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partition design in ovl and not ovl enabled new generic in aes.vhd: ovl_enable (boolean); copy of aes_pkg.vhd to integrate ovl functions; copy of tb_aes.vhd to integrate ovl function
12 years ago
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Make PSL compatible with simulation & synthesis
4 years ago
​
partition design in ovl and not ovl enabled new generic in aes.vhd: ovl_enable (boolean); copy of aes_pkg.vhd to integrate ovl functions; copy of tb_aes.vhd to integrate ovl function
12 years ago
​
Make PSL compatible with simulation & synthesis
4 years ago
​
​
partition design in ovl and not ovl enabled new generic in aes.vhd: ovl_enable (boolean); copy of aes_pkg.vhd to integrate ovl functions; copy of tb_aes.vhd to integrate ovl function
12 years ago
 
  1. set signals [list]
  2. lappend signals "top.tb_aes.s_reset"
  3. lappend signals "top.tb_aes.s_clk"
  4. lappend signals "top.tb_aes.s_validin_enc"
  5. lappend signals "top.tb_aes.s_acceptout_enc"
  6. lappend signals "top.tb_aes.s_key"
  7. lappend signals "top.tb_aes.s_datain"
  8. lappend signals "top.tb_aes.s_validout_enc"
  9. lappend signals "top.tb_aes.s_acceptin_enc"
  10. lappend signals "top.tb_aes.s_dataout_enc"
  11. set num_added [ gtkwave::addSignalsFromList $signals ]