T. Meissner
51d7b485b9
Make PSL compatible with simulation & synthesis
4 years ago
T. Meissner
0a7ed338d6
Use co-sim with openSSL to check AES enc VHDL implementation
4 years ago
T. Meissner
d16c247b5c
Add OSVVM as submodule
4 years ago
T. Meissner
491b4df54f
Move PSL stuff in generate block; add formal PSL code
4 years ago
T. Meissner
303bda25e4
Add CTR-AES VHDL design
* CTR-AES design with configurable Nonce length (64-96)
* Max. secure frame length is 2**(128-len(nonce))-1
4 years ago
T. Meissner
dce8396498
Refactoring; remove unused functions
4 years ago
T. Meissner
50aaca8c6c
Fix PSL cover directives
4 years ago
T. Meissner
b7b9f36c9b
Add CBCMAC-AES VHDL design
4 years ago
T. Meissner
28b2cd3856
Implement key schedule for encryption, finally
4 years ago
T. Meissner
b59791e8f3
Move VHDL library files in work directory
6 years ago
T. Meissner
77f87536c9
FSM optimizations; PSL enhancements
* Optimize setting of valid/data outputs to save
one cycle
* Replace not working PSL stable assertion by
seperate helper register and equal compare
6 years ago
T. Meissner
c400d2ef1b
Add PSL checkers, refactoring
* Add some simple PSL checkers & coverage to aes_enc & aes_dec
* Add generating of PSL coverage report
* Add report outputs to testbench
6 years ago
T. Meissner
735c411ff8
First working version of AES enc & dec
* Split enc & dec in separate units aes_enc & aes_dec
* Add component declarations to aes_pkg
* Key schedule isn't implemented yet
* Fixed round keys at the moment until key schedule is implemented
* Simple test of enc & dec
* New aes top level unit (empty at the moment)
* Renamed makefile to Makefile
6 years ago
T. Meissner
d8ca919f37
Fixed many incorrect implemented functions
6 years ago
T. Meissner
42a5eb9b1b
Minor refactoring & bugfixing
* Set VHDL standard to VHDL 2008
* Replace rcon() functuion by simple array constant
* Correct loop range in addroundkey() function
6 years ago
T. Meissner
27e06dff2c
Fix gmul() & (inv)mixcolums() functions
6 years ago
T. Meissner
517237cfec
Created Readme.md file
8 years ago
T. Meissner
2f91130184
Add remaining AES functions
* addroundkey()
* subword()
* rotword()
* rcon()
9 years ago
T. Meissner
46f1b9295b
merge last changes from amc mini repo
10 years ago
T. Meissner
8a9b30940e
integrate s1-s8() into one s() function with additional parameter s_table; convert lower to upper case
10 years ago
T. Meissner
313a08b6f3
add verilog simulation environment for cbcmac-des
10 years ago
T. Meissner
4dd3f74d15
Merge branch 'master' of https://github.com/tmeissner/cryptocores
10 years ago
T. Meissner
918483068b
add ITER define; add accept ports to des instance
10 years ago
T. Meissner
8f575798ea
add .PHONY to clean target
10 years ago
T. Meissner
3531c69ce1
add support for ITER & PIPE variations of DES verilog implementation
10 years ago
T. Meissner
9454ed15cd
removed assignments of c & d in r & l process reset state
10 years ago
T. Meissner
6dd9c4ad6c
removed wrong assignments of r in the c & d process
10 years ago
T. Meissner
cb14f089b9
add acceptin & acceptout ports
10 years ago
T. Meissner
b9efb85f01
add second iterative implementation; selection between the two implementations by #ifdef's
10 years ago
T. Meissner
a65d41bf93
add verilog version of CBCMAC with DES algorithm
10 years ago
T. Meissner
67df839c95
add implementation & testbench of CBCMAC with DES algorithm
10 years ago
T. Meissner
393757693e
add removing of testbench binary to clean target
10 years ago
T. Meissner
82ae83f1dc
adapted to ITER & PIPE configuration, supports now both settings
10 years ago
T. Meissner
af8fe6023d
add accept signals to waveform view
10 years ago
T. Meissner
cfd20a9bbc
add removing of object files to clean target
10 years ago
T. Meissner
5ded08aa7b
added GPLv2 license file
10 years ago
T. Meissner
80443e531d
internal mode is now a latched copy of mode_i (ITER)
10 years ago
T. Meissner
034386b0ce
removed forgotten data_o drivers from process
10 years ago
T. Meissner
1e53c62084
data_o is generated in parallel to sync process now
10 years ago
T. Meissner
5ebdae8b61
add iterative implementation; config via generic 'design_type'
10 years ago
T. Meissner
1d061d5dc5
Merge branch 'master' of https://github.com/tmeissner/cryptocores
11 years ago
T. Meissner
579eab1bf0
removed internal synced copy of reset_i; set ready to high in reset
11 years ago
T. Meissner
1d858ce952
added removing of tb_tdes binary and *.o files in clean target
11 years ago
T. Meissner
a83081760f
added prototype of addroundkey() function
11 years ago
T. Meissner
de08e53153
removed internal synced copy of reset_i; set ready to high in reset
11 years ago
T. Meissner
4b1f3d11f9
removed internal synced copy of reset_i; set ready to high in reset
11 years ago
T. Meissner
a91d55740a
wait for rising edge of s_reset before send stimuli data
11 years ago
T. Meissner
2a2aa23e21
wait for rising edge of reset before send stimuli data
11 years ago
T. Meissner
ad3f36bbec
Merge branch 'master' of https://github.com/tmeissner/cryptocores
11 years ago
T. Meissner
258e9db1e4
removed internal synced copy of reset; set ready to high in reset
11 years ago
