T. Meissner 51d7b485b9 | 4 years ago | |
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aes | 4 years ago | |
cbcdes | 11 years ago | |
cbcmac_aes/rtl/vhdl | 4 years ago | |
cbcmac_des | 10 years ago | |
cbctdes | 11 years ago | |
ctraes/rtl/vhdl | 4 years ago | |
des | 10 years ago | |
lib | 4 years ago | |
tdes | 11 years ago | |
.gitignore | 11 years ago | |
.gitmodules | 4 years ago | |
LICENSE.textile | 10 years ago | |
README.md | 4 years ago |
cryptography ip-cores in vhdl / verilog
The components in this repository are not intended for productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.
HINT:
The tests of some algorithms use the OSVVM library, which is redistributed as
submodule. To get & initialize the submodule, please use the --recursive
option
when cloning this repository.