cryptography ip-cores in vhdl / verilog

vhdl ghdl osvvm fpga testbenches verilog cryptography

T. Meissner 51d7b485b9 Make PSL compatible with simulation & synthesis		5 years ago
aes	Make PSL compatible with simulation & synthesis	5 years ago
cbcdes	moved array type definitions out of functions to head of package, instances now also in package head and are constants	11 years ago
cbcmac_aes/rtl/vhdl	Add CBCMAC-AES VHDL design	5 years ago
cbcmac_des	merge last changes from amc mini repo	10 years ago
cbctdes	removed internal synced copy of reset_i; set ready to high in reset	11 years ago
ctraes/rtl/vhdl	Add CTR-AES VHDL design	5 years ago
des	merge last changes from amc mini repo	10 years ago
lib	Add OSVVM as submodule	5 years ago
tdes	added removing of tb_tdes binary and *.o files in clean target	11 years ago
.gitignore	added ignore file	11 years ago
.gitmodules	Add OSVVM as submodule	5 years ago
LICENSE.textile	added GPLv2 license file	10 years ago
README.md	Use co-sim with openSSL to check AES enc VHDL implementation	5 years ago

README.md

cryptocores

cryptography ip-cores in vhdl / verilog

The components in this repository are not intended for productional code. They serve as proof of concept, for example how to implement a pipeline using only (local) variables instead of (global) signals. Furthermore they were used how to do a VHDL-to-Verilog conversion for learning purposes.

HINT:

The tests of some algorithms use the OSVVM library, which is redistributed as submodule. To get & initialize the submodule, please use the --recursive option when cloning this repository.