tmeissner
/
cryptocores
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
cryptography ip-cores in vhdl / verilog
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
195 Commits
1 Branch
1.7 MiB
Tree: 51d7b485b9
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '51d7b485b9'
${ noResults }
cryptocores/des/sim/vhdl/tb_des.tcl

12 lines
454 B
Raw Normal View History

moved vhdl testbench files into separate directory vhdl under sim
13 years ago
​
​
​
add accept signals to waveform view
10 years ago
moved vhdl testbench files into separate directory vhdl under sim
13 years ago
​
​
​
add accept signals to waveform view
10 years ago
moved vhdl testbench files into separate directory vhdl under sim
13 years ago
​
 
  1. set signals [list]
  2. lappend signals "top.tb_des.s_reset"
  3. lappend signals "top.tb_des.s_clk"
  4. lappend signals "top.tb_des.s_validin"
  5. lappend signals "top.tb_des.s_acceptout"
  6. lappend signals "top.tb_des.s_mode"
  7. lappend signals "top.tb_des.s_key"
  8. lappend signals "top.tb_des.s_datain"
  9. lappend signals "top.tb_des.s_validout"
  10. lappend signals "top.tb_des.s_acceptin"
  11. lappend signals "top.tb_des.s_dataout"
  12. set num_added [ gtkwave::addSignalsFromList $signals ]