cryptography ip-cores in vhdl / verilog
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  1. // ======================================================================
  2. // DES encryption/decryption
  3. // algorithm according:FIPS 46-3 specification
  4. // Copyright (C) 2012 Torsten Meissner
  5. //-----------------------------------------------------------------------
  6. // This program is free software; you can redistribute it and/or modify
  7. // it under the terms of the GNU General Public License as published by
  8. // the Free Software Foundation; either version 2 of the License, or
  9. // (at your option) any later version.
  10. //
  11. // This program is distributed in the hope that it will be useful,
  12. // but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. // GNU General Public License for more details.
  15. //
  16. // You should have received a copy of the GNU General Public License
  17. // along with this program; if not, write:the Free Software
  18. // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. // ======================================================================
  20. `timescale 1ns/1ps
  21. module des
  22. (
  23. input reset_i, // async reset
  24. input clk_i, // clock
  25. input mode_i, // des-mode: 0 = encrypt, 1 = decrypt
  26. input [0:63] key_i, // key input
  27. input [0:63] data_i, // data input
  28. input valid_i, // input key/data valid flag
  29. output reg [0:63] data_o, // data output
  30. output valid_o // output data valid flag
  31. );
  32. `include "../../rtl/verilog/des_pkg.v"
  33. // valid, mode register
  34. reg [0:18] valid;
  35. reg [0:17] mode;
  36. // algorithm pipeline register
  37. // key calculation register
  38. reg [0:27] c0;
  39. reg [0:27] c1;
  40. reg [0:27] c2;
  41. reg [0:27] c3;
  42. reg [0:27] c4;
  43. reg [0:27] c5;
  44. reg [0:27] c6;
  45. reg [0:27] c7;
  46. reg [0:27] c8;
  47. reg [0:27] c9;
  48. reg [0:27] c10;
  49. reg [0:27] c11;
  50. reg [0:27] c12;
  51. reg [0:27] c13;
  52. reg [0:27] c14;
  53. reg [0:27] c15;
  54. reg [0:27] c16;
  55. reg [0:27] d0;
  56. reg [0:27] d1;
  57. reg [0:27] d2;
  58. reg [0:27] d3;
  59. reg [0:27] d4;
  60. reg [0:27] d5;
  61. reg [0:27] d6;
  62. reg [0:27] d7;
  63. reg [0:27] d8;
  64. reg [0:27] d9;
  65. reg [0:27] d10;
  66. reg [0:27] d11;
  67. reg [0:27] d12;
  68. reg [0:27] d13;
  69. reg [0:27] d14;
  70. reg [0:27] d15;
  71. reg [0:27] d16;
  72. // key register
  73. wire [0:47] key1;
  74. wire [0:47] key2;
  75. wire [0:47] key3;
  76. wire [0:47] key4;
  77. wire [0:47] key5;
  78. wire [0:47] key6;
  79. wire [0:47] key7;
  80. wire [0:47] key8;
  81. wire [0:47] key9;
  82. wire [0:47] key10;
  83. wire [0:47] key11;
  84. wire [0:47] key12;
  85. wire [0:47] key13;
  86. wire [0:47] key14;
  87. wire [0:47] key15;
  88. wire [0:47] key16;
  89. // register for left, right data blocks
  90. reg [0:31] l;
  91. reg [0:31] l0;
  92. reg [0:31] l1;
  93. reg [0:31] l2;
  94. reg [0:31] l3;
  95. reg [0:31] l4;
  96. reg [0:31] l5;
  97. reg [0:31] l6;
  98. reg [0:31] l7;
  99. reg [0:31] l8;
  100. reg [0:31] l9;
  101. reg [0:31] l10;
  102. reg [0:31] l11;
  103. reg [0:31] l12;
  104. reg [0:31] l13;
  105. reg [0:31] l14;
  106. reg [0:31] l15;
  107. reg [0:31] l16;
  108. reg [0:31] r;
  109. reg [0:31] r0;
  110. reg [0:31] r1;
  111. reg [0:31] r2;
  112. reg [0:31] r3;
  113. reg [0:31] r4;
  114. reg [0:31] r5;
  115. reg [0:31] r6;
  116. reg [0:31] r7;
  117. reg [0:31] r8;
  118. reg [0:31] r9;
  119. reg [0:31] r10;
  120. reg [0:31] r11;
  121. reg [0:31] r12;
  122. reg [0:31] r13;
  123. reg [0:31] r14;
  124. reg [0:31] r15;
  125. reg [0:31] r16;
  126. wire valid_o = valid[18];
  127. // valid, mode register
  128. always @(posedge clk_i, negedge reset_i) begin
  129. if(~reset_i) begin
  130. valid <= 0;
  131. mode <= 0;
  132. end
  133. else begin
  134. // shift registers
  135. valid[1:18] <= valid[0:17];
  136. valid[0] <= valid_i;
  137. mode[1:17] <= mode[0:16];
  138. mode[0] <= mode_i;
  139. end
  140. end
  141. // des algorithm pipeline
  142. always @(posedge clk_i, negedge reset_i) begin
  143. if(~reset_i) begin
  144. l <= 0;
  145. r <= 0;
  146. l0 <= 0;
  147. l1 <= 0;
  148. l2 <= 0;
  149. l3 <= 0;
  150. l4 <= 0;
  151. l5 <= 0;
  152. l6 <= 0;
  153. l7 <= 0;
  154. l8 <= 0;
  155. l9 <= 0;
  156. l10 <= 0;
  157. l11 <= 0;
  158. l12 <= 0;
  159. l13 <= 0;
  160. l14 <= 0;
  161. l15 <= 0;
  162. l16 <= 0;
  163. r0 <= 0;
  164. r1 <= 0;
  165. r2 <= 0;
  166. r3 <= 0;
  167. r4 <= 0;
  168. r5 <= 0;
  169. r6 <= 0;
  170. r7 <= 0;
  171. r8 <= 0;
  172. r9 <= 0;
  173. r10 <= 0;
  174. r11 <= 0;
  175. r12 <= 0;
  176. r13 <= 0;
  177. r14 <= 0;
  178. r15 <= 0;
  179. r16 <= 0;
  180. data_o <= 0;
  181. end
  182. else begin
  183. // output stage
  184. data_o <= ipn({r16, l16});
  185. // 16. stage
  186. l16 <= r15;
  187. r16 <= l15 ^ (f(r15, key16));
  188. // 15. stage
  189. l15 <= r14;
  190. r15 <= l14 ^ (f(r14, key15));
  191. // 14. stage
  192. l14 <= r13;
  193. r14 <= l13 ^ (f(r13, key14));
  194. // 13. stage
  195. l13 <= r12;
  196. r13 <= l12 ^ (f(r12, key13));
  197. // 12. stage
  198. l12 <= r11;
  199. r12 <= l11 ^ (f(r11, key12));
  200. // 11. stage
  201. l11 <= r10;
  202. r11 <= l10 ^ (f(r10, key11));
  203. // 10. stage
  204. l10 <= r9;
  205. r10 <= l9 ^ (f(r9, key10));
  206. // 9. stage
  207. l9 <= r8;
  208. r9 <= l8 ^ (f(r8, key9));
  209. // 8. stage
  210. l8 <= r7;
  211. r8 <= l7 ^ (f(r7, key8));
  212. // 7. stage
  213. l7 <= r6;
  214. r7 <= l6 ^ (f(r6, key7));
  215. // 6. stage
  216. l6 <= r5;
  217. r6 <= l5 ^ (f(r5, key6));
  218. // 5. stage
  219. l5 <= r4;
  220. r5 <= l4 ^ (f(r4, key5));
  221. // 4. stage
  222. l4 <= r3;
  223. r4 <= l3 ^ (f(r3, key4));
  224. // 3. stage
  225. l3 <= r2;
  226. r3 <= l2 ^ (f(r2, key3));
  227. // 2. stage
  228. l2 <= r1;
  229. r2 <= l1 ^ (f(r1, key2));
  230. // 1. stage
  231. l1 <= r0;
  232. r1 <= l0 ^ (f(r0, key1));
  233. // 1. state
  234. l0 <= l;
  235. r0 <= r;
  236. // input stage
  237. l <= ip0(data_i);
  238. r <= ip1(data_i);
  239. end
  240. end
  241. // des key pipeline
  242. always @(posedge clk_i, negedge reset_i) begin
  243. if(~reset_i) begin
  244. c0 <= 0;
  245. c1 <= 0;
  246. c2 <= 0;
  247. c3 <= 0;
  248. c4 <= 0;
  249. c5 <= 0;
  250. c6 <= 0;
  251. c7 <= 0;
  252. c8 <= 0;
  253. c9 <= 0;
  254. c10 <= 0;
  255. c11 <= 0;
  256. c12 <= 0;
  257. c13 <= 0;
  258. c14 <= 0;
  259. c15 <= 0;
  260. c16 <= 0;
  261. d0 <= 0;
  262. d1 <= 0;
  263. d2 <= 0;
  264. d3 <= 0;
  265. d4 <= 0;
  266. d5 <= 0;
  267. d6 <= 0;
  268. d7 <= 0;
  269. d8 <= 0;
  270. d9 <= 0;
  271. d10 <= 0;
  272. d11 <= 0;
  273. d12 <= 0;
  274. d13 <= 0;
  275. d14 <= 0;
  276. d15 <= 0;
  277. d16 <= 0;
  278. end
  279. else begin
  280. // input stage
  281. c0 <= pc1_c(key_i);
  282. d0 <= pc1_d(key_i);
  283. // 1st stage
  284. if (~mode[0]) begin
  285. c1 <= {c0[1:27], c0[0]};
  286. d1 <= {c0[1:27], c0[0]};
  287. end
  288. else begin
  289. c1 <= c0;
  290. d1 <= d0;
  291. end
  292. // 2nd stage
  293. if (~mode[1]) begin
  294. c2 <= {c1[1:27], c1[0]};
  295. d2 <= {d1[1:27], d1[0]};
  296. end
  297. else begin
  298. c2 <= {c1[27], c1[0:26]};
  299. d2 <= {d1[27], d1[0:26]};
  300. end
  301. // 3rd stage
  302. if (~mode[2]) begin
  303. c3 <= {c2[2:27], c2[0:1]};
  304. d3 <= {d2[2:27], d2[0:1]};
  305. end
  306. else begin
  307. c3 <= {c2[26:27], c2[0:25]};
  308. d3 <= {d2[26:27], d2[0:25]};
  309. end
  310. // 4th stage
  311. if (~mode[3]) begin
  312. c4 <= {c3[2:27], c3[0:1]};
  313. d4 <= {d3[2:27], d3[0:1]};
  314. end
  315. else begin
  316. c4 <= {c3[26:27], c3[0:25]};
  317. d4 <= {d3[26:27], d3[0:25]};
  318. end
  319. // 5th stage
  320. if (~mode[4]) begin
  321. c5 <= {c4[2:27], c4[0:1]};
  322. d5 <= {d4[2:27], d4[0:1]};
  323. end
  324. else begin
  325. c5 <= {c4[26:27], c4[0:25]};
  326. d5 <= {d4[26:27], d4[0:25]};
  327. end
  328. // 6. stage
  329. if (~mode[5]) begin
  330. c6 <= {c5[2:27], c5[0:1]};
  331. d6 <= {d5[2:27], d5[0:1]};
  332. end
  333. else begin
  334. c6 <= {c5[26:27], c5[0:25]};
  335. d6 <= {d5[26:27], d5[0:25]};
  336. end
  337. // 7. stage
  338. if (~mode[6]) begin
  339. c7 <= {c6[2:27], c6[0:1]};
  340. d7 <= {d6[2:27], d6[0:1]};
  341. end
  342. else begin
  343. c7 <= {c6[26:27], c6[0:25]};
  344. d7 <= {d6[26:27], d6[0:25]};
  345. end
  346. // 8. stage
  347. if (~mode[7]) begin
  348. c8 <= {c7[2:27], c7[0:1]};
  349. d8 <= {d7[2:27], d7[0:1]};
  350. end
  351. else begin
  352. c8 <= {c7[26:27], c7[0:25]};
  353. d8 <= {d7[26:27], d7[0:25]};
  354. end
  355. // 9. stage
  356. if (~mode[8]) begin
  357. c9 <= {c8[2:27], c8[0:1]};
  358. d9 <= {d8[2:27], d8[0:1]};
  359. end
  360. else begin
  361. c9 <= {c8[26:27], c8[0:25]};
  362. d9 <= {d8[26:27], d8[0:25]};
  363. end
  364. // 10. stage
  365. if (~mode[9]) begin
  366. c10 <= {c9[2:27], c9[0:1]};
  367. d10 <= {d9[2:27], d9[0:1]};
  368. end
  369. else begin
  370. c10 <= {c9[26:27], c9[0:25]};
  371. d10 <= {d9[26:27], d9[0:25]};
  372. end
  373. // 6. stage
  374. if (~mode[10]) begin
  375. c11 <= {c10[2:27], c10[0:1]};
  376. d11 <= {d10[2:27], d10[0:1]};
  377. end
  378. else begin
  379. c11 <= {c10[26:27], c10[0:25]};
  380. d11 <= {d10[26:27], d10[0:25]};
  381. end
  382. // 6. stage
  383. if (~mode[11]) begin
  384. c12 <= {c11[2:27], c11[0:1]};
  385. d12 <= {d11[2:27], d11[0:1]};
  386. end
  387. else begin
  388. c12 <= {c11[26:27], c11[0:25]};
  389. d12 <= {d11[26:27], d11[0:25]};
  390. end
  391. // 6. stage
  392. if (~mode[12]) begin
  393. c13 <= {c12[2:27], c12[0:1]};
  394. d13 <= {d12[2:27], d12[0:1]};
  395. end
  396. else begin
  397. c13 <= {c12[26:27], c12[0:25]};
  398. d13 <= {d12[26:27], d12[0:25]};
  399. end
  400. // 6. stage
  401. if (~mode[13]) begin
  402. c14 <= {c13[2:27], c13[0:1]};
  403. d14 <= {d13[2:27], d13[0:1]};
  404. end
  405. else begin
  406. c14 <= {c13[26:27], c13[0:25]};
  407. d14 <= {d13[26:27], d13[0:25]};
  408. end
  409. // 6. stage
  410. if (~mode[14]) begin
  411. c15 <= {c14[2:27], c14[0:1]};
  412. d15 <= {d14[2:27], d14[0:1]};
  413. end
  414. else begin
  415. c15 <= {c14[26:27], c14[0:25]};
  416. d15 <= {d14[26:27], d14[0:25]};
  417. end
  418. // 6. stage
  419. if (~mode[15]) begin
  420. c16 <= {c15[1:27], c15[0]};
  421. d16 <= {d15[1:27], d15[0]};
  422. end
  423. else begin
  424. c16 <= {c15[27], c15[0:26]};
  425. d16 <= {d15[27], d15[0:26]};
  426. end
  427. end
  428. end
  429. // key assignments
  430. assign key1 = pc2({c1, d1});
  431. assign key2 = pc2({c2, d2});
  432. assign key3 = pc2({c3, d3});
  433. assign key4 = pc2({c4, d4});
  434. assign key5 = pc2({c5, d5});
  435. assign key6 = pc2({c6, d6});
  436. assign key7 = pc2({c7, d7});
  437. assign key8 = pc2({c8, d8});
  438. assign key9 = pc2({c9, d9});
  439. assign key10 = pc2({c10, d10});
  440. assign key11 = pc2({c11, d11});
  441. assign key12 = pc2({c12, d12});
  442. assign key13 = pc2({c13, d13});
  443. assign key14 = pc2({c14, d14});
  444. assign key15 = pc2({c15, d15});
  445. assign key16 = pc2({c16, d16});
  446. endmodule