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cryptocores
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12 Commits (bab578f2c6c33caff75384897c606e5c0face047)

Author SHA1 Message Date
  T. Meissner 4c7037b7c3 added timescale directive and set it to 1 ns/1 ps 12 years ago
  T. Meissner ccf8140132 complete refactoring of the des verilog code 12 years ago
  Torsten Meissner 74c974f956 further converting of vhdl into verilog code 13 years ago
  Torsten Meissner 270ac45e53 began with converting of implementation from vhdl to verilog 13 years ago
  Torsten Meissner 3399288adc change lib path for simulation 13 years ago
  Torsten Meissner 804a359af4 new synchronous process for mode & valid signals 13 years ago
  Torsten Meissner c1f59849e5 initial release of des function package in verilog 13 years ago
  Torsten Meissner 93186c5d1c initial release of des verilog implementation, framework code only at the moment 13 years ago
  Torsten Meissner 78db757f9d new verily version of ads, startup code only at the moment 13 years ago