Merge branch 'master' of https://github.com/tmeissner/cryptocores

des/rtl/verilog/des.v

@@ -19,6 +19,8 @@
 // ======================================================================
 
 
+`timescale 1ns/1ps
+
 
 module des
   (

des/sim/verilog/tb_des.tcl

@@ -7,5 +7,4 @@ lappend signals "tb_des.key"
 lappend signals "tb_des.datain"
 lappend signals "tb_des.validout"
 lappend signals "tb_des.dataout"
-lappend signals "tb_des.outdex"
 set num_added [ gtkwave::addSignalsFromList $signals ]

des/sim/verilog/tb_des.v

@@ -18,6 +18,8 @@
 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 // ======================================================================
 
+`timescale 1ns/1ps
+
 
 module tb_des;