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Merge pull request #1 from umarcor/ci/gha

ci: add GitHub Actions workflow 'test'
master
T. Meissner 4 years ago
committed by GitHub
parent
commit
e9f14349e6
No known key found for this signature in database GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 78 additions and 3 deletions
  1. +17
    -0
      .github/test.sh
  2. +57
    -0
      .github/workflows/test.yml
  3. +4
    -3
      aes/sim/vhdl/Makefile

+ 17
- 0
.github/test.sh View File

@ -0,0 +1,17 @@
#!/usr/bin/env sh
set -e
cd $(dirname "$0")/..
run_sim() {
echo "::group::Test $1"
cd "$1"/sim/vhdl
$MAKE sim
cd ../../..
echo '::endgroup::'
}
for item in aes cbcdes cbcmac_des cbctdes des tdes; do
run_sim $item
done

+ 57
- 0
.github/workflows/test.yml View File

@ -0,0 +1,57 @@
name: 'test'
on:
push:
pull_request:
jobs:
lin:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
with:
submodules: recursive
- name: Install dependencies
run: |
sudo apt update -qq
sudo apt install -y libssl-dev
- uses: ghdl/setup-ghdl-ci@master
with:
backend: llvm
- run: ./.github/test.sh
env:
MAKE: make
win:
runs-on: windows-latest
defaults:
run:
shell: msys2 {0}
steps:
- uses: msys2/setup-msys2@v2
with:
msystem: MINGW64
update: true
install: >
mingw-w64-x86_64-make
mingw-w64-x86_64-ghdl-llvm
mingw-w64-x86_64-openssl
- run: git config --global core.autocrlf input
shell: bash
- uses: actions/checkout@v2
with:
submodules: recursive
- run: ./.github/test.sh
env:
MAKE: mingw32-make

+ 4
- 3
aes/sim/vhdl/Makefile View File

@ -20,9 +20,10 @@
RTL_SRC := \ RTL_SRC := \
../../rtl/vhdl/aes_pkg.vhd \ ../../rtl/vhdl/aes_pkg.vhd \
../../rtl/vhdl/aes.vhd \
../../rtl/vhdl/aes_enc.vhd \ ../../rtl/vhdl/aes_enc.vhd \
../../rtl/vhdl/aes_dec.vhd
../../rtl/vhdl/aes_dec.vhd \
../../rtl/vhdl/aes.vhd
SIM_SRC := tb_aes.vhd SIM_SRC := tb_aes.vhd
C_SRC := tb_aes.c C_SRC := tb_aes.c
@ -72,7 +73,7 @@ tb_aes: ${RTL_SRC} ${SIM_SRC} ${C_SRC} osvvm/OsvvmContext.o | work
@echo "Analyze testbench & design ..." @echo "Analyze testbench & design ..."
ghdl -a --std=$(VHD_STD) -fpsl --workdir=work -P=osvvm ${RTL_SRC} ${SIM_SRC} ghdl -a --std=$(VHD_STD) -fpsl --workdir=work -P=osvvm ${RTL_SRC} ${SIM_SRC}
@echo "Elaborate testbench & design ..." @echo "Elaborate testbench & design ..."
ghdl -e --std=$(VHD_STD) -fpsl --workdir=work -P=osvvm -Wl,-lcrypto -Wl,-lssl -Wl,$@.c $@
ghdl -e --std=$(VHD_STD) -fpsl --workdir=work -P=osvvm -Wl,$@.c -Wl,-lcrypto -Wl,-lssl $@
tb_aes.ghw: tb_aes tb_aes.ghw: tb_aes


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