11 Commits (270ac45e53ab41716e7d61d37bbfe011bf38ef05)

Author SHA1 Message Date
  Torsten Meissner 270ac45e53 began with converting of implementation from vhdl to verilog 13 years ago
  Torsten Meissner 3399288adc change lib path for simulation 13 years ago
  Torsten Meissner 804a359af4 new synchronous process for mode & valid signals 13 years ago
  Torsten Meissner e1900a3e28 all necessary functions are complete now 13 years ago
  Torsten Meissner 69c7fe92f9 added functions s1 - s8 13 years ago
  Torsten Meissner c1f59849e5 initial release of des function package in verilog 13 years ago
  Torsten Meissner 93186c5d1c initial release of des verilog implementation, framework code only at the moment 13 years ago
  Torsten Meissner 1be72c73b6 Revert "New verily top level file of DES algorithm" 13 years ago
  Torsten Meissner 3ff9e3e269 New verily top level file of DES algorithm 13 years ago
  Torsten Meissner 0b1ef754eb Revert "move vhdl files into separate directory" 13 years ago
  Torsten Meissner fdc730de69 move vhdl files into separate directory 13 years ago