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cryptocores
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9 Commits (5fff1d89d1c9a96a42f18a0fa1f89ab47e7686b4)

Author SHA1 Message Date
  T. Meissner e2225fbbc9 initial commit os TDES verilog design file 12 years ago
  T. Meissner 45403f17d1 import of des verilog design files 12 years ago
  T. Meissner d779f5aebe moved into seperate vhdl folder 12 years ago
  T. Meissner 7822728a74 moved into seperate vhdl folder 12 years ago
  Torsten Meissner 4b8ab0d0cc added async reset to des-module to avoid simulation warnings and unititialized ports 14 years ago
  Torsten Meissner e1c9cb244b fixed some bugs with the key suppliment 14 years ago
  Torsten Meissner aec8130bdc some minor bugfixes 14 years ago
  Torsten Meissner 25f37f7d9e Revision 0.1 2011/10/08 14 years ago
  Torsten Meissner 2a0a9348f3 Revision 0.1 2011/10/08 14 years ago