cryptocores

1.7 MiB

Author	SHA1	Message	Date
T. Meissner	5640e7884b	Update CBCDES unit and tests * Use des from des dir instead of local copies * Adapt testbench to des interface * Add Makefile for VHDL-synthesis	5 years ago
T. Meissner	716ce2725b	moved array type definitions out of functions to head of package, instances now also in package head and are constants	12 years ago
T. Meissner	f76ae71dd3	beauty care	13 years ago
T. Meissner	4489748aec	initial commit os CBCDES verilog design file	13 years ago
T. Meissner	c42beff5b8	moved vhdl design files in directory 'vhdl'	13 years ago
T. Meissner	ab47fd3a54	import verilog des design files from des project	13 years ago
T. Meissner	6356f624af	moved vhdl design files in directory 'vhdl'	13 years ago
Torsten Meissner	4b8ab0d0cc	added async reset to des-module to avoid simulation warnings and unititialized ports	14 years ago
Torsten Meissner	5f440e10ad	Revision 0.2 2011/10/06 corrected some bugs which were found while testing cbc ability	14 years ago
Torsten Meissner	b9ed938d6d	register mode_i and iv_i only if start_i is high	14 years ago
Torsten Meissner	5c4b112411	Initial Release of CBC-DES cbcdes.vhd and tb_cbcdes.vhd are still incomplete, maybe they contain some bugs	14 years ago