T. Meissner
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4c7037b7c3
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added timescale directive and set it to 1 ns/1 ps
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12 years ago |
T. Meissner
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ccf8140132
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complete refactoring of the des verilog code
* now 2 seperate processes: key scheduling & data path
* keys are now concurrent wire assignments
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12 years ago |
T. Meissner
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08f7c16e5d
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fixed some errors in des helper functions
* functions s1() - s8() returned incorrect slices of the matrix
* function s2() had one incorrect nibble in cause of faulty conversion
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12 years ago |
Torsten Meissner
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74c974f956
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further converting of vhdl into verilog code
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13 years ago |
Torsten Meissner
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5bf2207f11
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splitting function ip to 2 sub functions ip0 & ip1
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13 years ago |
Torsten Meissner
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270ac45e53
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began with converting of implementation from vhdl to verilog
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13 years ago |
Torsten Meissner
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3399288adc
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change lib path for simulation
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13 years ago |
Torsten Meissner
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804a359af4
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new synchronous process for mode & valid signals
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13 years ago |
Torsten Meissner
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e1900a3e28
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all necessary functions are complete now
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13 years ago |
Torsten Meissner
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69c7fe92f9
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added functions s1 - s8
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13 years ago |
Torsten Meissner
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c1f59849e5
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initial release of des function package in verilog
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13 years ago |
Torsten Meissner
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93186c5d1c
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initial release of des verilog implementation, framework code only at the moment
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13 years ago |
Torsten Meissner
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1be72c73b6
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Revert "New verily top level file of DES algorithm"
This reverts commit 3ff9e3e269 .
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13 years ago |
Torsten Meissner
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3ff9e3e269
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New verily top level file of DES algorithm
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13 years ago |
Torsten Meissner
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0b1ef754eb
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Revert "move vhdl files into separate directory"
This reverts commit fdc730de69 .
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13 years ago |
Torsten Meissner
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fdc730de69
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move vhdl files into separate directory
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13 years ago |