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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdlghdlosvvmfpgatestbenchesverilogcryptography
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223 Commits
1 Branch
1.7 MiB
VHDL 51.3%
Verilog 33.4%
Makefile 10.2%
C 3.5%
Tcl 1.5%
 
 
 
 
 
Branch: master
master
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Create branch ${ searchTerm }
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${ noResults }
cryptocores/cbcdes/sim/verilog
History
T. Meissner b6fdf6bbd4 initial commit of cbcdes verilog verification sources 12 years ago
..
data_input.txt initial commit of cbcdes verilog verification sources 12 years ago
data_output.txt initial commit of cbcdes verilog verification sources 12 years ago
key_input.txt initial commit of cbcdes verilog verification sources 12 years ago
makefile initial commit of verilog simulation environment for verilog cbcdes core 12 years ago
tb_cbcdes.tcl initial commit of cbcdes verilog verification sources 12 years ago
tb_cbcdes.v initial commit of cbcdes verilog verification sources 12 years ago
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