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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdlghdlosvvmfpgatestbenchesverilogcryptography
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119 Commits
1 Branch
1.7 MiB
VHDL 51.3%
Verilog 33.4%
Makefile 10.2%
C 3.5%
Tcl 1.5%
 
 
 
 
 
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T. Meissner 0c70ec5653 initial commit of verilog simulation environment for verilog cbcdes core 12 years ago
aes new verily version of ads, startup code only at the moment 13 years ago
cbcdes initial commit of verilog simulation environment for verilog cbcdes core 12 years ago
cbctdes remove OVL support in older, finished & verified projects 14 years ago
des correct some copy & paste errors in key scheduling process 12 years ago
tdes bugfixes to make tdes.v core working correctly 12 years ago
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