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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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211
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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17ce27949f
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cryptocores
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des
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sim
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vhdl
History
T. Meissner
393757693e
add removing of testbench binary to clean target
10 years ago
..
makefile
add removing of testbench binary to clean target
10 years ago
tb_des.tcl
add accept signals to waveform view
10 years ago
tb_des.vhd
adapted to ITER & PIPE configuration, supports now both settings
10 years ago