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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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215
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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cryptocores
/
cbctdes
History
T. Meissner
e3e993fe4b
Add Makefile for synthesis of CBCTDES
4 years ago
..
rtl
removed internal synced copy of reset_i; set ready to high in reset
11 years ago
sim
wait for rising edge of s_reset before send stimuli data
11 years ago
syn/
vhdl
Add Makefile for synthesis of CBCTDES
4 years ago