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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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187
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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28b2cd3856
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cryptocores
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cbcmac_des
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rtl
History
T. Meissner
46f1b9295b
merge last changes from amc mini repo
10 years ago
..
verilog
add ITER define; add accept ports to des instance
10 years ago
vhdl
merge last changes from amc mini repo
10 years ago