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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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221
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1
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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cryptocores
/
des
History
T. Meissner
81df6e0215
Update & restructure DES testbench to use openSSL and random simuli
4 years ago
..
rtl
Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring
4 years ago
sim
Update & restructure DES testbench to use openSSL and random simuli
4 years ago
syn/
vhdl
Add more VHDL-synthesis Makefiles; use src of des instead of local copies; minor refactoring
4 years ago