ci: rename 'test' workflow to 'Simulation'

* Fix counter init & increase enable to prevent aes_enc PSL assume error
* Add CTR-AES testbench, at the moment without data checks

ci: add GitHub Actions workflow 'test'

* Use des from des dir instead of local copies
* Adapt testbench to des interface
* Add Makefile for VHDL-synthesis

* CTR-AES design with configurable Nonce length (64-96)
* Max. secure frame length is 2**(128-len(nonce))-1

* Optimize setting of valid/data outputs to save
  one cycle
* Replace not working PSL stable assertion by
  seperate helper register and equal compare

* Add some simple PSL checkers & coverage to aes_enc & aes_dec
* Add generating of PSL coverage report
* Add report outputs to testbench

* Split enc & dec in separate units aes_enc & aes_dec
* Add component declarations to aes_pkg
* Key schedule isn't implemented yet
* Fixed round keys at the moment until key schedule is implemented
* Simple test of enc & dec
* New aes top level unit (empty at the moment)
* Renamed makefile to Makefile

* Set VHDL standard to VHDL 2008
* Replace rcon() functuion by simple array constant
* Correct loop range in addroundkey() function

* addroundkey()
* subword()
* rotword()
* rcon()