tmeissner
/
cryptocores
1
0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
cryptography ip-cores in vhdl / verilog
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
95 Commits
1 Branch
1.7 MiB
 
 
 
 
 
Tree: 4c7037b7c3
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '4c7037b7c3'
${ noResults }
cryptocores/des/sim/verilog
T. Meissner 9a340f5524 added timescale directive and set it to 1 ns/1 ps 12 years ago
..
data_input.txt stimuli.txt moved to data_input.txt 12 years ago
data_output.txt new verification data files key_input.txt & data_output.txt 12 years ago
key_input.txt new verification data files key_input.txt & data_output.txt 12 years ago
makefile dependency files now moved into 2 variables SRC_FILES & SIM_FILES 12 years ago
tb_des.tcl removed 'outdex' reg from waveform viewer 12 years ago
tb_des.v added timescale directive and set it to 1 ns/1 ps 12 years ago