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121 lines
3.9 KiB
121 lines
3.9 KiB
-- ======================================================================
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-- CTR-AES
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-- Copyright (C) 2020 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.aes_pkg.all;
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entity ctraes is
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generic (
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NONCE_WIDTH : natural range 64 to 96 := 96
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);
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port (
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reset_i : in std_logic; -- low active async reset
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clk_i : in std_logic; -- clock
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start_i : in std_logic; -- start ctr
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nonce_i : in std_logic_vector(0 to NONCE_WIDTH-1); -- nonce
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key_i : in std_logic_vector(0 to 127); -- key input
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data_i : in std_logic_vector(0 to 127); -- data input
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valid_i : in std_logic; -- input key/data valid flag
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accept_o : out std_logic; -- input accept
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data_o : out std_logic_vector(0 tO 127); -- data output
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valid_o : out std_logic; -- output data valid flag
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accept_i : in std_logic -- output accept
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);
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end entity ctraes;
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architecture rtl of ctraes is
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signal s_aes_datain : std_logic_vector(data_i'range);
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signal s_aes_dataout : std_logic_vector(data_o'range);
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signal s_aes_key : std_logic_vector(key_i'range);
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signal s_key : std_logic_vector(key_i'range);
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signal s_nonce : std_logic_vector(nonce_i'range);
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signal s_data_in : std_logic_vector(data_i'range);
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signal s_counter : unsigned(0 to 127-NONCE_WIDTH);
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begin
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s_aes_key <= key_i when start_i = '1' else s_key;
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s_aes_datain <= nonce_i & (s_counter'range => '0') when start_i = '1' else
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s_nonce & std_logic_vector(s_counter);
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data_o <= s_aes_dataout xor s_data_in;
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inputreg : process (clk_i, reset_i) is
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begin
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if (reset_i = '0') then
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s_key <= (others => '0');
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s_nonce <= (others => '0');
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s_data_in <= (others => '0');
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elsif (rising_edge(clk_i)) then
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if (valid_i = '1' and accept_o = '1') then
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s_data_in <= data_i;
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if (start_i = '1') then
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s_key <= key_i;
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s_nonce <= nonce_i;
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end if;
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end if;
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end if;
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end process inputreg;
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counterreg : process (clk_i, reset_i) is
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begin
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if (reset_i = '0') then
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s_counter <= (others => '0');
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elsif (rising_edge(clk_i)) then
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if (valid_i = '1' and accept_o = '1' and start_i = '1') then
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s_counter <= (others => '0');
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elsif (valid_o = '1' and accept_i = '1') then
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s_counter <= s_counter + 1;
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end if;
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end if;
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end process counterreg;
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i_aes : aes_enc
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generic map (
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design_type => "ITER"
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)
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port map (
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reset_i => reset_i,
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clk_i => clk_i,
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key_i => s_aes_key,
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data_i => s_aes_datain,
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valid_i => valid_i,
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accept_o => accept_o,
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data_o => s_aes_dataout,
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valid_o => valid_o,
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accept_i => accept_i
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);
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end architecture rtl;
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