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cryptography ip-cores in vhdl / verilog
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cryptocores/cbcdes
Torsten Meissner 5b924ff4e2 expanded simulation time to 200 us for decryption testcases 13 years ago
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rtl register mode_i and iv_i only if start_i is high 13 years ago
sim expanded simulation time to 200 us for decryption testcases 13 years ago