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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
10.2%
C
3.5%
Tcl
1.5%
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cryptocores
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cbcdes
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sim
History
Torsten Meissner
5b924ff4e2
expanded simulation time to 200 us for decryption testcases
13 years ago
..
makefile
expanded simulation time to 200 us for decryption testcases
13 years ago
tb_cbcdes.vhd
Revision 1.1 2011/09/25
13 years ago