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tmeissner
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cryptocores
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cryptography ip-cores in vhdl / verilog
vhdl
ghdl
osvvm
fpga
testbenches
verilog
cryptography
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1.7 MiB
VHDL
51.3%
Verilog
33.4%
Makefile
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C
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Tcl
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Torsten Meissner
8909aa0d9a
expanded simulation time to 100 us for encryption testcases
13 years ago
cbcdes
expanded simulation time to 100 us for encryption testcases
13 years ago
des
I mean the test vases in NIST document 800-17 ;-)
13 years ago