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628 lines
23 KiB
628 lines
23 KiB
-- ======================================================================
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-- DES encryption/decryption
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-- algorithm according to FIPS 46-3 specification
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-- Copyright (C) 2007 Torsten Meissner
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-------------------------------------------------------------------------
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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-- ======================================================================
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.des_pkg.all;
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entity des is
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generic (
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design_type : string := "ITER"
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);
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port (
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reset_i : in std_logic; -- async reset
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clk_i : IN std_logic; -- clock
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mode_i : IN std_logic; -- des-modus: 0 = encrypt, 1 = decrypt
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key_i : IN std_logic_vector(0 TO 63); -- key input
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data_i : IN std_logic_vector(0 TO 63); -- data input
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valid_i : IN std_logic; -- input key/data valid
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accept_o : out std_logic; -- input data accepted
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data_o : OUT std_logic_vector(0 TO 63); -- data output
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valid_o : OUT std_logic; -- output data valid flag
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accept_i : in std_logic
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);
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end entity des;
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architecture rtl of des is
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begin
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PipeG : if design_type = "PIPE" generate
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begin
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crypt : PROCESS (clk_i, reset_i) IS
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-- variables for key calculation
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VARIABLE c0 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c1 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c2 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c3 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c4 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c5 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c6 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c7 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c8 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c9 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c10 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c11 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c12 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c13 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c14 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c15 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE c16 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d0 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d1 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d2 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d3 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d4 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d5 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d6 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d7 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d8 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d9 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d10 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d11 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d12 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d13 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d14 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d15 : std_logic_vector(0 TO 27) := (others => '0');
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VARIABLE d16 : std_logic_vector(0 TO 27) := (others => '0');
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-- key variables
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VARIABLE key1 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key2 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key3 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key4 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key5 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key6 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key7 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key8 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key9 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key10 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key11 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key12 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key13 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key14 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key15 : std_logic_vector(0 TO 47) := (others => '0');
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VARIABLE key16 : std_logic_vector(0 TO 47) := (others => '0');
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-- variables for left & right data blocks
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VARIABLE l0 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l1 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l2 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l3 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l4 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l5 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l6 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l7 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l8 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l9 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l10 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l11 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l12 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l13 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l14 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l15 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE l16 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r0 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r1 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r2 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r3 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r4 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r5 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r6 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r7 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r8 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r9 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r10 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r11 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r12 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r13 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r14 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r15 : std_logic_vector( 0 TO 31) := (others => '0');
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VARIABLE r16 : std_logic_vector( 0 TO 31) := (others => '0');
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-- variables for mode & valid shift registers
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VARIABLE mode : std_logic_vector(0 TO 16) := (others => '0');
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VARIABLE valid : std_logic_vector(0 TO 17) := (others => '0');
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BEGIN
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if(reset_i = '0') then
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data_o <= (others => '0');
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valid_o <= '0';
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elsif rising_edge( clk_i ) THEN
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-- shift registers
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valid(1 TO 17) := valid(0 TO 16);
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valid(0) := valid_i;
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mode(1 TO 16) := mode(0 TO 15);
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mode(0) := mode_i;
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-- output stage
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accept_o <= '1';
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valid_o <= valid(17);
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data_o <= ipn( ( r16 & l16 ) );
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-- 16. stage
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IF mode(16) = '0' THEN
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c16 := c15(1 TO 27) & c15(0);
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d16 := d15(1 TO 27) & d15(0);
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ELSE
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c16 := c15(27) & c15(0 TO 26);
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d16 := d15(27) & d15(0 TO 26);
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END IF;
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key16 := pc2( ( c16 & d16 ) );
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l16 := r15;
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r16 := l15 xor ( f( r15, key16 ) );
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-- 15. stage
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IF mode(15) = '0' THEN
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c15 := c14(2 TO 27) & c14(0 TO 1);
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d15 := d14(2 TO 27) & d14(0 TO 1);
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ELSE
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c15 := c14(26 TO 27) & c14(0 TO 25);
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d15 := d14(26 TO 27) & d14(0 TO 25);
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END IF;
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key15 := pc2( ( c15 & d15 ) );
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l15 := r14;
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r15 := l14 xor ( f( r14, key15 ) );
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-- 14. stage
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IF mode(14) = '0' THEN
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c14 := c13(2 TO 27) & c13(0 TO 1);
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d14 := d13(2 TO 27) & d13(0 TO 1);
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ELSE
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c14 := c13(26 TO 27) & c13(0 TO 25);
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d14 := d13(26 TO 27) & d13(0 TO 25);
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END IF;
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key14 := pc2( ( c14 & d14 ) );
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l14 := r13;
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r14 := l13 xor ( f( r13, key14 ) );
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-- 13. stage
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IF mode(13) = '0' THEN
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c13 := c12(2 TO 27) & c12(0 TO 1);
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d13 := d12(2 TO 27) & d12(0 TO 1);
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ELSE
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c13 := c12(26 TO 27) & c12(0 TO 25);
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d13 := d12(26 TO 27) & d12(0 TO 25);
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END IF;
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key13 := pc2( ( c13 & d13 ) );
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l13 := r12;
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r13 := l12 xor ( f( r12, key13 ) );
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-- 12. stage
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IF mode(12) = '0' THEN
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c12 := c11(2 TO 27) & c11(0 TO 1);
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d12 := d11(2 TO 27) & d11(0 TO 1);
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ELSE
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c12 := c11(26 TO 27) & c11(0 TO 25);
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d12 := d11(26 TO 27) & d11(0 TO 25);
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END IF;
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key12 := pc2( ( c12 & d12 ) );
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l12 := r11;
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r12 := l11 xor ( f( r11, key12 ) );
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-- 11. stage
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IF mode(11) = '0' THEN
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c11 := c10(2 TO 27) & c10(0 TO 1);
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d11 := d10(2 TO 27) & d10(0 TO 1);
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ELSE
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c11 := c10(26 TO 27) & c10(0 TO 25);
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d11 := d10(26 TO 27) & d10(0 TO 25);
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END IF;
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key11 := pc2( ( c11 & d11 ) );
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l11 := r10;
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r11 := l10 xor ( f( r10, key11 ) );
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-- 10. stage
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IF mode(10) = '0' THEN
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c10 := c9(2 TO 27) & c9(0 TO 1);
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d10 := d9(2 TO 27) & d9(0 TO 1);
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ELSE
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c10 := c9(26 TO 27) & c9(0 TO 25);
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d10 := d9(26 TO 27) & d9(0 TO 25);
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END IF;
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key10 := pc2( ( c10 & d10 ) );
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l10 := r9;
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r10 := l9 xor ( f( r9, key10 ) );
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-- 9. stage
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IF mode(9) = '0' THEN
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c9 := c8(1 TO 27) & c8(0);
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d9 := d8(1 TO 27) & d8(0);
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ELSE
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c9 := c8(27) & c8(0 TO 26);
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d9 := d8(27) & d8(0 TO 26);
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END IF;
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key9 := pc2( ( c9 & d9 ) );
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l9 := r8;
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r9 := l8 xor ( f( r8, key9 ) );
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-- 8. stage
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IF mode(8) = '0' THEN
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c8 := c7(2 TO 27) & c7(0 TO 1);
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d8 := d7(2 TO 27) & d7(0 TO 1);
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ELSE
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c8 := c7(26 TO 27) & c7(0 TO 25);
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d8 := d7(26 TO 27) & d7(0 TO 25);
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END IF;
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key8 := pc2( ( c8 & d8 ) );
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l8 := r7;
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r8 := l7 xor ( f( r7, key8 ) );
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-- 7. stage
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IF mode(7) = '0' THEN
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c7 := c6(2 TO 27) & c6(0 TO 1);
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d7 := d6(2 TO 27) & d6(0 TO 1);
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ELSE
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c7 := c6(26 TO 27) & c6(0 TO 25);
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d7 := d6(26 TO 27) & d6(0 TO 25);
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END IF;
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key7 := pc2( ( c7 & d7 ) );
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l7 := r6;
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r7 := l6 xor ( f( r6, key7 ) );
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-- 6. stage
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IF mode(6) = '0' THEN
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c6 := c5(2 TO 27) & c5(0 TO 1);
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d6 := d5(2 TO 27) & d5(0 TO 1);
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ELSE
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c6 := c5(26 TO 27) & c5(0 TO 25);
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d6 := d5(26 TO 27) & d5(0 TO 25);
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END IF;
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key6 := pc2( ( c6 & d6 ) );
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l6 := r5;
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r6 := l5 xor ( f( r5, key6 ) );
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-- 5. stage
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IF mode(5) = '0' THEN
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c5 := c4(2 TO 27) & c4(0 TO 1);
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d5 := d4(2 TO 27) & d4(0 TO 1);
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ELSE
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c5 := c4(26 TO 27) & c4(0 TO 25);
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d5 := d4(26 TO 27) & d4(0 TO 25);
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END IF;
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key5 := pc2( ( c5 & d5 ) );
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l5 := r4;
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r5 := l4 xor ( f( r4, key5 ) );
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-- 4. stage
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IF mode(4) = '0' THEN
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c4 := c3(2 TO 27) & c3(0 TO 1);
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d4 := d3(2 TO 27) & d3(0 TO 1);
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ELSE
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c4 := c3(26 TO 27) & c3(0 TO 25);
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d4 := d3(26 TO 27) & d3(0 TO 25);
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END IF;
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key4 := pc2( ( c4 & d4 ) );
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l4 := r3;
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r4 := l3 xor ( f( r3, key4 ) );
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-- 3. stage
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IF mode(3) = '0' THEN
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c3 := c2(2 TO 27) & c2(0 TO 1);
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d3 := d2(2 TO 27) & d2(0 TO 1);
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ELSE
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c3 := c2(26 TO 27) & c2(0 TO 25);
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d3 := d2(26 TO 27) & d2(0 TO 25);
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END IF;
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key3 := pc2( ( c3 & d3 ) );
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l3 := r2;
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r3 := l2 xor ( f( r2, key3 ) );
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-- 2. stage
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IF mode(2) = '0' THEN
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c2 := c1(1 TO 27) & c1(0);
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d2 := d1(1 TO 27) & d1(0);
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ELSE
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c2 := c1(27) & c1(0 TO 26);
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d2 := d1(27) & d1(0 TO 26);
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END IF;
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key2 := pc2( ( c2 & d2 ) );
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l2 := r1;
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r2 := l1 xor ( f( r1, key2 ) );
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-- 1. stage
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IF mode(1) = '0' THEN
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c1 := c0(1 TO 27) & c0(0);
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d1 := d0(1 TO 27) & d0(0);
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ELSE
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c1 := c0;
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d1 := d0;
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END IF;
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key1 := pc2( ( c1 & d1 ) );
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l1 := r0;
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r1 := l0 xor ( f( r0, key1 ) );
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-- input stage
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l0 := ip( data_i )(0 TO 31);
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r0 := ip( data_i )(32 TO 63);
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c0 := pc1_c( key_i );
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d0 := pc1_d( key_i );
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END IF;
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END PROCESS crypt;
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end generate PipeG;
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AreaG : if design_type = "ITER" generate
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signal s_accept : std_logic;
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signal s_valid : std_logic;
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signal s_l : std_logic_vector( 0 to 31);
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signal s_r : std_logic_vector( 0 to 31);
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begin
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cryptP : process (clk_i, reset_i) is
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variable v_c : std_logic_vector(0 to 27);
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variable v_d : std_logic_vector(0 to 27);
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variable v_key : std_logic_vector(0 to 47);
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variable v_mode : std_logic;
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variable v_rnd_cnt : natural;
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begin
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if(reset_i = '0') then
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v_c := (others => '0');
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v_d := (others => '0');
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v_key := (others => '0');
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s_l <= (others => '0');
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s_r <= (others => '0');
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v_rnd_cnt := 0;
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v_mode := '0';
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s_accept <= '0';
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s_valid <= '0';
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elsif rising_edge(clk_i) then
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case v_rnd_cnt is
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-- input stage
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when 0 =>
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s_accept <= '1';
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s_valid <= '0';
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if (valid_i = '1' and s_accept = '1') then
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s_accept <= '0';
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s_valid <= '0';
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s_l <= ip(data_i)(0 to 31);
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s_r <= ip(data_i)(32 to 63);
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v_c := pc1_c(key_i);
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v_d := pc1_d(key_i);
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v_mode := mode_i;
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v_rnd_cnt := v_rnd_cnt + 1;
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end if;
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-- stage 1
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when 1 =>
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if (v_mode = '0') then
|
|
v_c := v_c(1 to 27) & v_c(0);
|
|
v_d := v_d(1 to 27) & v_d(0);
|
|
end if;
|
|
v_key := pc2((v_c & v_d));
|
|
s_l <= s_r;
|
|
s_r <= s_l xor (f(s_r, v_key));
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 2 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(1 to 27) & v_c(0);
|
|
v_d := v_d(1 to 27) & v_d(0);
|
|
else
|
|
v_c := v_c(27) & v_c(0 to 26);
|
|
v_d := v_d(27) & v_d(0 to 26);
|
|
end if;
|
|
v_key := pc2((v_c & v_d));
|
|
s_l <= s_r;
|
|
s_r <= s_l xor (f(s_r, v_key));
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 3 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 4 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 5 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 6 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 7 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 8 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 9 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(1 to 27) & v_c(0);
|
|
v_d := v_d(1 to 27) & v_d(0);
|
|
else
|
|
v_c := v_c(27) & v_c(0 to 26);
|
|
v_d := v_d(27) & v_d(0 to 26);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 10 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 11 =>
|
|
-- 11. stage
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 12 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 13 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 14 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 15 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(2 to 27) & v_c(0 to 1);
|
|
v_d := v_d(2 to 27) & v_d(0 to 1);
|
|
else
|
|
v_c := v_c(26 to 27) & v_c(0 to 25);
|
|
v_d := v_d(26 to 27) & v_d(0 to 25);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 16 =>
|
|
if (v_mode = '0') then
|
|
v_c := v_c(1 to 27) & v_c(0);
|
|
v_d := v_d(1 to 27) & v_d(0);
|
|
else
|
|
v_c := v_c(27) & v_c(0 to 26);
|
|
v_d := v_d(27) & v_d(0 to 26);
|
|
end if;
|
|
v_key := pc2( ( v_c & v_d ) );
|
|
s_l <= s_r;
|
|
s_r <= s_l xor ( f( s_r, v_key ) );
|
|
v_rnd_cnt := v_rnd_cnt + 1;
|
|
|
|
when 17 =>
|
|
s_valid <= '1';
|
|
if (s_valid = '1') then
|
|
if(accept_i = '1') then
|
|
s_valid <= '0';
|
|
v_rnd_cnt := 0;
|
|
end if;
|
|
end if;
|
|
|
|
when others =>
|
|
null;
|
|
|
|
end case;
|
|
end if;
|
|
end process cryptP;
|
|
|
|
valid_o <= s_valid;
|
|
accept_o <= s_accept;
|
|
data_o <= ipn(s_r & s_l) when s_valid = '1' else (others => '0');
|
|
|
|
end generate AreaG;
|
|
|
|
|
|
|
|
END ARCHITECTURE rtl;
|