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cryptography ip-cores in vhdl / verilog
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cryptocores/des/sim
T. Meissner 9a340f5524 added timescale directive and set it to 1 ns/1 ps 12 years ago
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verilog added timescale directive and set it to 1 ns/1 ps 12 years ago
vhdl moved vhdl testbench files into separate directory vhdl under sim 13 years ago